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| RS8953B/8953SPB HDSL Channel Unit The RS8953B is a High-Bit-Rate Digital Subscriber Line (HDSL) channel unit designed to perform data, clock, and format conversions necessary to construct a Pulse Code Multiplexed (PCM) channel from one, two, or three HDSL channels. The PCM channel consists of transmit and receive data, clock and frame sync signals configured for standard T1 (1544 kbps), standard E1 (2048 kbps), or custom (Nx64 kbps) formats. The PCM channel connects directly to a Bt8370 T1/E1 Controller or similar T1/E1 device. Connection to other network/subscriber physical layer devices is supported by the custom PCM frame format. Three identical HDSL channel interfaces consist of serial data and clock connected to a Bt8970 HDSL Transceiver or similar 2B1Q bit pump device. The RS8953SPB contains one HDSL channel interface. Control and status registers are accessed via the Microprocessor Unit (MPU) interface. One common register group configures the PCM interface formatter, Pseudo-Random Bit Sequence (PRBS) generator, Bit Error Rate (BER) meter, timeslot router, Digital Phase Lock Loop (DPLL) clock recovery, and PCM Loopbacks (LB). Three groups of HDSL channel registers configure the elastic store FIFOs, overhead MUXes, receive framers, payload mappers, and HDSL loopbacks. Status registers monitor received overhead, DPLL, FIFO, and framer operations, including CRC and FEBE error counts. The RS8953B adheres to Bellcore TA-NWT-001210 and FA-NWT-001211 and the latest ETSI RTR/TM-03036 standards. C-language software for all standard T1/E1 configuration and startup procedures is implemented on Conexant's HDSL Evaluation Module (Bt8973EVM) and is available under a no-fee license agreement. RS8953B software can also be developed for non-standard HDSL applications or to interoperate with existing HDSL equipment. Distinguishing Features Supports All HDSL Bit Rates - 2 pair T1 standard (784 kbps) - 2 pair E1 standard (1168 kbps) - 3 pair E1 standard (784 kbps) - 1/2/3 pair custom (Nx64 kbps, N=2-36) * T1/E1 Primary Rate (PCM) Channel - Connects to Conexant E1/T1 Framers - Framed or unframed mode - Sync/Async payload mapping - Clock recovery/jitter attenuation - PRBS/fixed test patterns - BER measurement * HDSL Channels - Connects to Conexant ZipWire Transceivers - Three independent serial channels - Central, remote, or repeater - Overhead (HOH) management - Programmable path delays - Error performance monitoring - Software controlled EOC and IND - Auxiliary payload/Z-bit data link - Master loop ID and interchange - Auto tip/ring reversal * Programmable Data Routing - PCM timeslots - HDSL payload - Drop/Insert - HDSL payload - Auxiliary - HDSL payload - PRBS/Fixed - PCM or HDSL - PCM and HDSL loopbacks * Intel(R) or Motorola(R) MPU interface * CMOS technology, 3.3 V operation * 68-pin PLCC or 80-pin PQFP * Functional Block Diagram Timeslot Router PCM Formatter Drop Insert Elastic Store Mapper HOH Mux 2B1Q Encoder HDSL Channels 1, 2, 3 PRBS LB BER Stuff LB PCM Channel Elastic Store Payload Mapper 2B1Q Decoder Applications * * * * * * * * Full, Fractional or Multipoint T1/E1 Single and Multichannel Repeaters Voice Pair Gain Systems Wireless LAN/PBX PCS, Cellular Base Station Fiber Access/Distribution Loop Carrier, Remote Switches Subscriber Line Modem MPU Registers DPLL Receive Framer Microprocessor PLL Filter Data Sheet D8953BDSB March 30, 1999 Ordering Information Order Number RS8953BEPF RS8953BEPJ RS8953SPB EPF RS8953SPB EPJ Package 80-Pin Plastic Quad Flat Pack (PQFP) 68-Pin Plastic Leaded Chip Carrier (PLCC) 80-Pin Plastic Quad Flat Pack (PQFP) 68-Pin Plastic Leaded Chip Carrier (PLCC) Number of HDSL Channels 3 3 1 1 Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. Conexant and "What's Next in Communications Technologies" are trademarks of Conexant Systems, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. (c) 1999 Conexant Systems, Inc. Printed in U.S.A. All Rights Reserved Reader Response: To improve the quality of our publications, we welcome your feedback. Please send comments or suggestions via e-mail to Conexant Reader Response@conexant.com. Sorry, we can't answer your technical questions at this address. Please contact your local Conexant sales office or local field applications engineer if you have technical questions. D8953BDSB Conexant Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii 1.0 HDSL Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 HTU Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.2 Repeaters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Fractional Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Switching Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Loop Carrier/Pair Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Point-to-Multipoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Subscriber Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 2.0 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 2.2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 3.0 Circuit Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.2.1 Address/Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 3-3 3-3 PCM Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PCM Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.1.1 Transmit Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.1.2 Transmit Routing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.1.3 PRBS Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.1.4 Drop/Insert Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.1.5 TFIFO Water Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PCM Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.2 N8953BDSB Conexant iii Table of Contents RS8953B/8953SPB HDSL Channel Unit 3.2.2.1 3.2.2.2 3.2.2.3 3.2.2.4 Receive Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Receive Combination Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 BER Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 RFIFO Water Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.3 3.4 3.5 Clock Recovery DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 HDSL Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.5.1 HDSL Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.5.1.1 Transmit Payload Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.5.1.2 HOH Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.5.1.3 CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.5.1.4 Scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.5.1.5 STUFF Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.5.1.6 2B1Q Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.5.1.7 HDSL Auxiliary Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 HDSL Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.5.2.1 2B1Q Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.5.2.2 HDSL Receive Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.5.2.3 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.5.2.4 CRC Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.5.2.5 HOH Demux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.5.2.6 Receive Payload Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.5.2.7 HDSL Auxiliary Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Transferring Data from HDSL to RSER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions of Detection Algorithms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inserting Data Transferred from HDSL to RSER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transferring Data from TSER to HDSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inserting Data Transferred from TSER to HDSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 3.6 PRA Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3-34 3-35 3-35 3-35 3-36 4.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 4.1 4.2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 HDSL Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 iv Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Table of Contents 0x00--Transmit Embedded Operations Channel (TEOC_LO) . . . . . . . . . . . . . . . . . . . . . 5-10 0x01--Transmit Embedded Operations Channel (TEOC_HI) . . . . . . . . . . . . . . . . . . . . . . 5-10 0x02--Transmit Indicator Bits (TIND_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 0x03--Transmit Indicator Bits (TIND_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 0x04--Transmit Z-Bits (TZBIT_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 0xDF--Transmit Z-Bits (TZBIT_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 0xE0--Transmit Z-Bits (TZBIT_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 0xE1--Transmit Z-Bits (TZBIT_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 0xE2--Transmit Z-Bits (TZBIT_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 0xE3--Transmit Z-Bits (TZBIT_6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 0x05--Transmit FIFO Water Level (TFIFO_WL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 0x06--Transmit Command Register 1 (TCMD_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 0x07--Transmit Command Register 2 (TCMD_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 4.3 Transmit Payload Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 0x08--Transmit Payload Map (TMAP_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 0x09--Transmit Payload Map (TMAP_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 0x0A--Transmit Payload Map (TMAP_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 0x0B--Transmit Payload Map (TMAP_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 0x0C--Transmit Payload Map (TMAP_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 0x0F--Transmit Payload Map (TMAP_6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 0x10--Transmit Payload Map (TMAP_7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 0x11--Transmit Payload Map (TMAP_8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 0x12--Transmit Payload Map (TMAP_9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 0x0D--Transmit FIFO Reset (TFIFO_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 0x0E--Scrambler Reset (SCR_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 4.4 HDSL Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 0x60--Receive Command Register 1 (RCMD_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x61--Receive Command Register 2 (RCMD_2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x62--Receive Elastic Store FIFO Reset (RFIFO_RST). . . . . . . . . . . . . . . . . . . . . . . . . . 0x63--Receive Framer Synchronization Reset (SYNC_RST) . . . . . . . . . . . . . . . . . . . . . 4.5 0x64--Receive Payload Map (RMAP_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x65--Receive Payload Map (RMAP_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x66--Receive Payload Map (RMAP_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x69--Receive Payload Map (RMAP_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x6A--Receive Payload Map (RMAP_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x6B--Receive Payload Map (RMAP_6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x67--Error Count Reset (ERR_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0x68--Receive Signaling Location (RSIG_LOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 5-19 5-20 5-21 5-21 5-22 5-22 5-22 5-22 5-22 5-23 5-23 5-23 Receive Payload Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 PCM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 0xC0--TSER Frame Bit Location (TFRAME_LOC_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 0xC1--TSER Frame Bit Location (TFRAME_LOC_HI). . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 N8953BDSB Conexant v Table of Contents RS8953B/8953SPB HDSL Channel Unit 0xC2--TSER Multiframe Bit Location (TMF_LOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 0xC3--RSER Frame Bit Location (RFRAME_LOC_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 0xC4--RSER Frame Bit Location (RFRAME_LOC_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 0xC5--RSER Multiframe Bit Location (RMF_LOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 0xC6--PCM Multiframe Length (MF_LEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 0xC7--PCM Multiframes per HDSL Frame (MF_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 0xC8--PCM Frame Length (FRAME_LEN_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 0xC9--PCM Frame Length (FRAME_LEN_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 4.7 HDSL Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 0xCA--HDSL Frame Length (HFRAME_LEN_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xF5--HDSL Frame Length (HFRAME_LEN_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xF8--HDSL Frame Length (HFRAME2_LEN_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xF9--HDSL Frame Length (HFRAME2_LEN_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xFA--HDSL Frame Length (HFRAME3_LEN_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xFB--HDSL Frame Length (HFRAME3_LEN_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xCB--SYNC Word A (SYNC_WORD_A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xCC--SYNC Word B (SYNC_WORD_B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xCD--RX FIFO Water Level (RFIFO_WL_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xCE--RX FIFO Water Level (RFIFO_WL_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5-30 5-30 5-30 5-30 5-31 5-31 5-31 5-31 5-32 5-33 5-33 5-33 5-33 5-33 5-34 4.8 Transmit Bit Stuffing Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 0xCF--Bit Stuffing Threshold A (STF_THRESH_A_LO) . . . . . . . . . . . . . . . . . . . . . . . . . 0xD0--Bit Stuffing Threshold A (STF_THRESH_A_HI). . . . . . . . . . . . . . . . . . . . . . . . . . 0xD1--Bit Stuffing Threshold B (STF_THRESH_B_LO) . . . . . . . . . . . . . . . . . . . . . . . . . 0xD2--Bit Stuffing Threshold B (STF_THRESH_B_HI). . . . . . . . . . . . . . . . . . . . . . . . . . 0xD3--Bit Stuffing Threshold C (STF_THRESH_C_LO) . . . . . . . . . . . . . . . . . . . . . . . . . 0xD4--Bit Stuffing Threshold C (STF_THRESH_C_HI). . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 DPLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 0xD5--DPLL Residual (DPLL_RESID_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 0xD6--DPLL Residual (DPLL_RESID_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 0xD7--DPLL Factor (DPLL_FACTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 0xD8--DPLL Gain (DPLL_GAIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 0xDB--DPLL Phase Detector Init (DPLL_PINI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 0xF6--Reset DPLL Phase Detector (DPLL_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 4.10 Data Path Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 0xDC--Data Bank Pattern 1 (DBANK_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 0xDD--Data Bank Pattern 2 (DBANK_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 0xDE--Data Bank Pattern 3 (DBANK_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 0xEA--Fill Pattern (FILL_PATT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 0xE4--Transmit Stuff Bit Value (TSTUFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 0xED--Transmit Routing Table (ROUTE_TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 0xEE--Receive Combination Table (COMBINE_TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 0xF2--Receive Signaling Table (RSIG_TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 4.11 Common Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 0xE5--Command Register 1 (CMD_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 0xE6--Command Register 2 (CMD_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 vi Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 0xE7--Command Register 3 (CMD_3) 0xE8--Command Register 4 (CMD_4) 0xE9--Command Register 5 (CMD_5) 0xF3--Command Register 6 (CMD_6) 0xF4--Command Register 7 (CMD_7) Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5-51 5-51 5-52 5-52 5-52 4.12 Interrupt and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 0xEB--Interrupt Mask Register (IMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xEC--Interrupt Clear Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xEF--Reset BER Meter/Start BER Measurement (BER_RST) . . . . . . . . . . . . . . . . . . . . 0xF0--Reset PRBS Generator (PRBS_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0xF1--Reset Receiver (RX_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Receive/Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 0x00--Receive Embedded Operations Channel (REOC_LO) . . . . . . . . . . . . . . . . . . . . . . 5-53 0x01--Receive Embedded Operations Channel (REOC_HI) . . . . . . . . . . . . . . . . . . . . . . 5-54 0x02--Receive Indicator Bits (RIND_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 0x03--Receive Indicator Bits (RIND_HI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 0x04--Receive Z-Bits (RZBIT_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 0x18--Receive Z-Bits (RZBIT_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 0x19--Receive Z-Bits (RZBIT_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 0x1A--Receive Z-Bits (RZBIT_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 0x1B--Receive Z-Bits (RZBIT_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 0x1C--Receive Z-Bits (RZBIT_6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 0x05--Receive Status 1 (STATUS_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 0x06--Receive Status 2 (STATUS_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 0x07--Transmit Status (STATUS_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 0x21--CRC Error Count (CRC_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 0x22--Far End Block Error Count (FEBE_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59 4.14 Common Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 0x1D--Bit Error Rate Meter (BER_METER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 0x1E--BER Status (BER_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61 0x1F--Interrupt Request Register (IRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61 0x28--DPLL Residual Output (RESID_OUT_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 0x20--DPLL Residual Output (RESID_OUT_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 0x30--Interrupt Mask Register (IMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 0x38--DPLL Phase Error (PHS_ERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 0x39--Multiframe Sync Phase Low (MSYNC_PHS_LO) . . . . . . . . . . . . . . . . . . . . . . . . 5-63 0x3A--Multiframe Sync Phase High (MSYNC_PHS_HI) . . . . . . . . . . . . . . . . . . . . . . . . 5-63 0x3B--Shadow Write (SHADOW_WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 0x3C--Error Status (ERR_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 4.15 PRA Transmit Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 0x40--PRA Transmit Control Register 0 (TX_PRA_CTRL0) . . . . . . . . . . . . . . . . . . . . . . 5-65 0x41--PRA Transmit Control Register 1 (TX_PRA_CTRL1) . . . . . . . . . . . . . . . . . . . . . . 5-66 N8953BDSB Conexant vii Table of Contents RS8953B/8953SPB HDSL Channel Unit 0x42--PRA Transmit Monitor Register 1 (TX _PRA_MON1) . . . . . . . . . . . . . . . . . . . . . 0x43--PRA Transmit E-Bits Counter (TX _PRA_E_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 0x45--PRA Transmit In-Band Code (TX_PRA_CODE) . . . . . . . . . . . . . . . . . . . . . . . . . . 0x46--PRA Transmit Monitor Register 0 (TX_PRA_MON0) . . . . . . . . . . . . . . . . . . . . . . 0x47--PRA Transmit Monitor Register 2 (TX_PRA_MON2) . . . . . . . . . . . . . . . . . . . . . . 0x70--PRA Transmit Control Register 0 (TX_PRA_CTRL0) . . . . . . . . . . . . . . . . . . . . . . 0x71--PRA Transmit Control Register 1 (TX_PRA_CTRL1) . . . . . . . . . . . . . . . . . . . . . . 0x72--PRA Transmit Bits Buffer 1 (TX_BITS_BUFF1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0x73--PRA Transmit TMSYNC offset Register (TX_PRA_TMSYNC_OFFSET) . . . . . . . . . 0x74--PRA Transmit Bits Buffer 0 (TX_BITS_BUFF0) . . . . . . . . . . . . . . . . . . . . . . . . . . 0x80--PRA Receive Control Register 0 (RX_PRA_CTRL0) . . . . . . . . . . . . . . . . . . . . . . 0x81--PRA Receive Control Register 1 (RX_PRA_CTRL1) . . . . . . . . . . . . . . . . . . . . . . 0x82--PRA Receive Monitor Register 1 (RX _PRA_MON1) . . . . . . . . . . . . . . . . . . . . . . 0x83--PRA Receive E bits Counter (RX_PRA_E_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 0x84--PRA Receive CRC4 Errors Counter (RX_PRA_CRC_CNT) . . . . . . . . . . . . . . . . . . 0x85--PRA Receive In-Band Code (RX_PRA_CODE). . . . . . . . . . . . . . . . . . . . . . . . . . . 0x86--PRA Receive Monitor Register 0 (RX_PRA_MON0) . . . . . . . . . . . . . . . . . . . . . . 0x87--PRA Receive Monitor Register 2 (RX_PRA_MON2) . . . . . . . . . . . . . . . . . . . . . . 0xB0--PRA Receive Control Register 0 (RX_PRA_CTRL0) . . . . . . . . . . . . . . . . . . . . . . 0xB1--PRA Receive Control Register 1 (RX_PRA_CTRL1) . . . . . . . . . . . . . . . . . . . . . . 0xB2--PRA Receive Bits Buffer 1 (RX_BITS_BUFF1). . . . . . . . . . . . . . . . . . . . . . . . . . . 0xB4--PRA Receive Bits Buffer 0 (RX_BITS_BUFF0). . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 5-67 5-67 5-68 5-68 5-69 5-70 5-71 5-71 5-72 5-73 5-74 5-75 5-75 5-75 5-76 5-76 5-76 5-77 5-78 5-79 5-79 4.16 PRA Transmit Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 4.17 PRA Receive Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 4.18 PRA Receive Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77 5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 5.1 5.2 5.3 5.4 5.5 Interfacing to a Conexant HDSL Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Interfacing to the Bt8370 E1/T1 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Interfacing to the 68302 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Interfacing to the 8051 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.0 Electrical and Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 MPU Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.0 Acronyms, Abbreviations and Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 7.1 Arithmetic Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 viii Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 7.1.1 7.1.2 Table of Contents Bit Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Differences Between Bt8953A and RS8953B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B: Bt8953A/RS8953B Product Bulletin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1 BCLK Phase Constraints In Repeater Mode; Non-Conformance Product Affected: Bt8953A and RS8953B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 N8953BDSB Conexant ix Table of Contents RS8953B/8953SPB HDSL Channel Unit x Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit List of Figures List of Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 3-18. Figure 3-19. Figure 3-20. Figure 3-21. Figure 3-22. Figure 3-23. Figure 3-24. Figure 3-25. Figure 3-26. HTU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Repeater System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Drop/Insert System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Switch/Mux System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Voice (Pairgain/Cellular/PCS) System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Point-to-Multipoint (Fractional) System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Subscriber Modem (Terminal) System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 RS8953B System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Three-Pair PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Single-Pair PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Three-Pair PQFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Single-Pair PQFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 MPU Bus Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 MPU Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 PCM Channel Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PCM Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 PCM Transmit Sync Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 PCM Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Drop/Insert Channel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 TFIFO Water Level Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PCM Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 PCM Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 PCM Receive Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 PRBS/BER Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 RFIFO Water Level Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 PCM and HDSL Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 2T1 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 2E1 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3E1 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 HDSL Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 HDSL Auxiliary Channel Payload Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 HDSL Auxiliary Channel Z-bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 HDSL Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 HDSL Receive Framer Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 Threshold Correlation Effect on Expected Sync Locations. . . . . . . . . . . . . . . . . . . . . . . . . 3-31 HDSL Auxiliary Receive Payload Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 HDSL Auxiliary Receive Z-bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 N8953BDSB Conexant xi List of Figures RS8953B/8953SPB HDSL Channel Unit Figure 3-27. Figure 4-1. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8. Figure 6-9. An Overview of the PRA Transfer of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 Transmit Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 RS8953B HDSL Channel Unit to Conexant HDSL Transceiver Interconnection . . . . . . . . . . 6-2 RS8953B HDSL Channel Unit to Bt8360 DS1 Framer Interconnection . . . . . . . . . . . . . . . . 6-3 RS8953B to 68302 Processor Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 RS8953B HDSL Channel Unit to 8051 Controller Interconnection . . . . . . . . . . . . . . . . . . . 6-5 Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Output Clock and Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 MPU Write Timing, MPUSEL = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 MPU Read Timing, MPUSEL = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 MPU Write Timing, MPUSEL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 MPU Read Timing, MPUSEL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 68-Pin PLCC Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 80-Pin PQFP Mechanical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 xii Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit List of Tables List of Tables Table 2-1. Table 2-2. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table 4-12. Table 4-13. Table 4-14. Table 4-15. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 6-6. Table 6-7. Table 6-8. Table 6-9. Table 6-10. Table A-1. Table A-2. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 PCM And HDSL Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 HDSL Frame Structure and Overhead Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 HDSL Frame Mapping Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 2B1Q Encoder Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 Z-Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 2B1Q Decoder Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 Register Summary Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 HDSL Transmit Write Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 HDSL Receive Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 PCM Formatter Write Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 HDSL Channel Configuration Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 DPLL Configuration Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 Data Path Options Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 Common Command Write Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 Interrupt and Reset Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 Receive and Transmit Status Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 Common Status Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 PRA Transmit Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 PRA Transmit Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 PRA Receive Read Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 PRA Receive Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Data Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Input Clock Edge Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Clock and Data Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Output Clock Edge Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 MPU Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 MPU Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 N8953BDSB Conexant xiii List of Tables RS8953B/8953SPB HDSL Channel Unit xiv Conexant N8953BDSB 1 1.0 HDSL Systems 1.1 HTU Applications The High-Bit-Rate Digital Subscriber Line (HDSL) is a simultaneous full-duplex transmission scheme which uses twisted-pair wire cables as the physical medium to transport signals between standard types of network or subscriber communication interfaces. A complete HDSL system consists of two pieces of terminal equipment connected by 1, 2, or 3 wire pairs. Each HDSL Terminal Unit (HTU) translates standard interface signals into HDSL payload for transmission, and reconstructs the standard interface from received payload. Bellcore standards define a 1.544 Mbps T1 transport application that uses two HDSL wire pairs (2T1), each operating at 784 kpbs. ETSI standards define a 2.048 Mbps E1 transport application using either two wire pairs (2E1), each operating at 1168 kpbs, or three wire pairs (3E1), each operating at 784 kpbs. N8953BDSB Conexant 1-1 1.0 HDSL Systems 1.1 HTU Applications RS8953B/RS8953SPB HDSL Channel Unit Figure 1-1 illustrates how an HDSL Terminal Unit (HTU) transports standard T1/E1 signals. T1/E1 transceivers convert T1/E1 interface signals into a Pulse Code Multiplexed (PCM) channel of clock, serial data, and optional frame sync. ZipWire transceivers convert 2B1Q line signals to HDSL channels of clock, serial data, and quat sync. The RS8953B translates between PCM and HDSL by performing PCM timeslot and HDSL payload routing, data scrambling and descrambling, overhead insertion and extraction, clock synchronization and clock synthesis. The Microprocessor Unit (MPU) configures devices for the intended application, manages overhead protocol, and monitors real-time performance. Figure 1-1. HTU Block Diagram HDSL Channel 1 PCM Channel T1/E1 Transceiver ZipWire Transceiver CH1 RS8953B HDSL Channel Unit HDSL Channel 2 ZipWire Transceiver CH2 MPU Bus MPU HDSL Channel 3 ZipWire Transceiver CH3 1.1.1 Repeaters Figure 1-2 shows single pair repeaters placed in line between HDSL terminals to extend transmission distance. RS8953B provides an internal cross-connect path between HDSL channels 1 and 2 to support single pair repeaters. Figure 1-2. Repeater System Block Diagram CH1 CH3 CH2 RS8953B PCM 1-2 Conexant N8953BDSB RS8953B/RS8953SPB HDSL Channel Unit 1.0 HDSL Systems 1.1 HTU Applications 1.1.2 Fractional Transport Figure 1-3 illustrates a drop/insert application where only a portion of the PCM channel bandwidth is transported over one or more HDSL wire pairs. The RS8953B provides drop/insert indicator signals to control external data MUXes and internal routing tables to map timeslots from either one of two synchronized PCM data sources. For remote terminals using partial payloads, the PCM channel may be configured to operate either at the standard interface rate or at the Nx64 effective payload rate. Figure 1-3. Drop/Insert System Block Diagram Insert T1/E1 FIBER or Other Transceiver Drop Mux D/I PCM RS8953B HDSL Channel Unit Mux T1/E1 FIBER or Other Transceiver HDSL CH1 HDSL CH2 Optional HDSL CH3 N8953BDSB Conexant 1-3 1.0 HDSL Systems 1.1 HTU Applications RS8953B/RS8953SPB HDSL Channel Unit 1.1.3 Switching Systems Figure 1-4 illustrates how the RS8953B is incorporated into a digital switch or multiplexer system that uses multiple HDSL lines to transport Nx64 or standard T1/E1 applications. The RS8953B's PCM timeslot router contains 64 table entries that extends the maximum PCM channel rate to 64x64 or 4.096 Mbps. RS8953B allows PCM channels at the central office (CO) and remote ends to operate at different rates. For example, the PCM channel in a digital switch may connect to a 4.096 Mbps shelf bus, while the remote terminal connects to a T1/E1 standard PCM channel. Figure 1-4. Switch/Mux System Block Diagram DS0 Switch Matrix SLIP BUFFER Nx64 RS8953B Nx64 SLIP BUFFER RS8953B CH1 CH2 CH3 CH1 CH2 CH3 NOTE(S): SLIP BUFFER = Optional frame SLIP BUFFER to align receive PCM with local master frame. 1-4 Conexant N8953BDSB RS8953B/RS8953SPB HDSL Channel Unit 1.0 HDSL Systems 1.1 HTU Applications 1.1.4 Loop Carrier/Pair Gain Figure 1-5 shows a channel bank application where the PCM channel connects a bank of voice and/or data subscriber line interfaces using an Nx64 bus. The total number of subscriber lines determines the PCM channel rate and determines how many HDSL wire pairs are needed to transport the application up to the digital loop carrier, cellular base station, network distribution element, or to the private branch exchange. The RS8953B supplies the PCM frame sync reference and acts as the PCM bus master for the remote channel bank. The RS8953B's Digital Phase Locked Loop (DPLL) clock recovery allows PCM channel rates down to 2x64 or 128 kpbs. Unpopulated PCM timeslots or HDSL payload bytes can be replaced by an 8-bit programmable fixed pattern, or one of four Pseudo-Random Bit Sequence (PRBS) patterns. Figure 1-5. Voice (Pairgain/Cellular/PCS) System Block Diagram Nx64 Bus SLI 1 CH1 Loop, Access, or Distribution Node RS8953B CH2 Optional SLI n CH3 NOTE(S): SLI = Subscriber Line Interface N8953BDSB Conexant 1-5 1.0 HDSL Systems 1.1 HTU Applications RS8953B/RS8953SPB HDSL Channel Unit 1.1.5 Point-to-Multipoint Figure 1-6 shows fractional T1/E1 services delivered from the CO to multiple remote sites in a Point-to-Multipoint (P2MP) application. The number of HDSL wire pairs and PCM channel rates at each site is variable. The RS8953B provides the ability to measure and compensate for misalignment between separate PCM frame syncs coming from each remote site. By programming transmit delays from PCM to HDSL frame syncs, each remote site can send its HDSL frames back to the central office. The HDSL frames are then sufficiently aligned with the others to be reconstructed into a single PCM frame at the central site. The RS8953B accommodates large differential delays associated with the P2MP application. It receives HDSL frame offsets to groom Channel Associated Signaling (CAS) from different sites. P2MP applications of primary rate ISDN transport are also supported, where different LAPD channels are received from each remote site. The RS8953B provides auxiliary HDSL channel inputs and outputs for the system to externally insert and monitor transmitted or received HDSL payload bytes. Auxiliary HDSL channels may alternately be configured to terminate the last 40 Z-bits through an external data link controller. Figure 1-6. Point-to-Multipoint (Fractional) System Block Diagram LAPD Signaling or Management Protocol SCC Aux1 SCC Aux2 SCC Aux3 Optional Site A CH1 CH1 RS8953B Partial T1/E1 Site B CH1 RS8953B Partial T1/E1 Full T1/E1 RS8953B CH2 CH3 CH1 Site C RS8953B Partial T1/E1 NOTE(S): 1. SCC = Serial Communications Controller 2. LAPD = Link Access Procedure D-Channel 3. AUX = Auxiliary HDSL channel attaches to payload or Z-bits 1-6 Conexant N8953BDSB RS8953B/RS8953SPB HDSL Channel Unit 1.0 HDSL Systems 1.1 HTU Applications 1.1.6 Subscriber Modem Figure 1-7 shows an HDSL data modem application where a CPU processor delivers PCM data directly to the RS8953B. Alternately, a multichannel communications controller such as the Bt8071A can be used to manage the transfer of data between the CPU and PCM channel through a local shared memory. Figure 1-7. Subscriber Modem (Terminal) System Block Diagram Single Channel Payload CH1 Serial Port RS8953B CH2 Optional Memory CH3 CPU Multichannel Payload CH1 Bt8071A 32-Channel HDLC Controller Shared Memory CPU RS8953B PCM CH2 Optional CH3 N8953BDSB Conexant 1-7 1.0 HDSL Systems 1.2 System Interfaces RS8953B/RS8953SPB HDSL Channel Unit 1.2 System Interfaces System interfaces and associated signals for the RS8953B functional circuit blocks are shown in Figure 1-8. Circuit blocks are described in sections 3 and 4, and signals are defined in Table 2-2. The single-pair version (RS8953SPBEPF and RS8953SPBEPJ) only supports HDSL Channel 1. HDSL Channels 2 and 3 are not usable. Although only 1 HDSL channel is usable, the internal registers are not changed from the 3 HDSL channel versions. The single-pair versions (RS8953SPBEPF and RS8953SPBEPJ) only supports HDSL Channel 1. HDSL Channels 2 and 3 are not usable. Although only 1 HDSL channel is usable, the internal registers are not changed from the 3 HDSL channel versions. This means that the registers should be programmed with the same value as if only HDSL channel 1 was used in a 3 channel version. This allows the 3 channel version to be used for development, and without a software change, a single-pair version used for production. Figure 1-8. RS8953B System Interfaces INSDAT INSERT DROP TCLK TSER TMSYNC MSYNC EXCLK RSER RMSYNC TAUX3 TLOAD3 RAUX3 ROH3 DPLL HDSL Channel3 BCLK3 QCLK3 TDAT3 RDAT3 PCM Channel TAUX2 TLOAD2 RAUX2 ROH2 HDSL Channel2 BCLK2 QCLK2 TDAT2 RDAT2 TAUX1 TLOAD1 RAUX1 ROH1 HDSL Channel1 BCLK1 QCLK1 TDAT1 RDAT1 MCLK RCLK SCLK INTR* RST* MPUSEL MPU Interface Test Access TCK TDI TDO TMS AD[7:0] 1-8 Conexant WR* CS* ALE RD* N8953BDSB 2 2.0 Pin Descriptions 2.1 Pin Assignments The RS8953B pin assignments for the 68-pin Plastic Leaded Chip Carrier (PLCC) package are shown in Figure 2-1 and Figure 2-2. The RS8953B pin assignments for the 80-pin Plastic Quad Flat Pack (PQFP) are shown in Figure 2-3 and Figure 2-4. The pinouts for RS8953B packages are listed in Table 2-1 and defined in Table 2-2. The input/output (I/O) column in Table 2-1 is coded as follows: I = Input, O = Output, I/O = Bidirectional, VCC = Power, GND = Ground, and NC = No Connection. N8953BDSB Conexant 2-1 2.0 Pin Descriptions 2.1 Pin Assignments RS8953B/8953SPB HDSL Channel Unit Figure 2-1. Three-Pair PLCC Pin Assignments QCLK1 TDAT1 ROH1 BCLK1 GND RDAT2 TDAT2 BCLK2 GND QCLK2 ROH2 QCLK3 GND BCLK3 RDAT3 ROH3 VCC RDAT1 AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] VCC EXCLK INSDAT INSERT/RAUX2 INTR* TMSYNC RMSYNC GND 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RS8953BEPJ TDAT3 SCLK MSYNC/RAUX3 TAUX3 TAUX2 TAUX1 TLOAD3 TLOAD2 TLOAD1 WR* ALE VCC PLLVCC PLLDGND PLLAGND VEXT VCC 2-2 VCC MPUSEL TCLK RCLK TSER RSER RD* RST* TCK TDI TDO TMS GND DROP/RAUX1 CS* MCLK VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Figure 2-2. Single-Pair PLCC Pin Assignments QCLK1 TDAT1 ROH1 BCLK1 GND NC NC NC GND NC NC NC GND NC NC NC VCC 2.0 Pin Descriptions 2.1 Pin Assignments RDAT1 AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] VCC EXCLK INSDAT INSERT(1) INTR* TMSYNC RMSYNC GND 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RS8953SPBEPJ NC SCLK MSYNC(1) NC NC TAUX1 NC NC TLOAD1 WR* ALE VCC PLLVCC PLLDGND PLLAGND VEXT VCC NOTE(S): (1) These pins are only functional when RAUX_EN is not active (RAUX_EN = 0). N8953BDSB VCC MPUSEL TCLK RCLK TSER RSER RD* RST* TCK TDI TDO TMS GND DROP/RAUX1 CS* MCLK VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Conexant 2-3 2.0 Pin Descriptions 2.1 Pin Assignments RS8953B/8953SPB HDSL Channel Unit Figure 2-3. Three-Pair PQFP Pin Assignments MSYNC/RAUX3 PLLDGND PLLAGND TLOAD3 TLOAD2 TLOAD1 PLLVCC TAUX3 TAUX2 TAUX1 TDAT3 ROH3 VCC VEXT SCLK VCC VCC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 RDAT3 BCLK3 GND QCLK3 ROH2 QCLK2 GND GND BCLK2 NC TDAT2 RDAT2 GND BCLK1 ROH1 TDAT1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 QCLK1 2 NC 3 RDAT1 4 NC 56 AD[0] AD[1] 7 AD[2] 8 AD[3] 9 AD[4] 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 INTR* GND GND AD[7] VCC VCC NC INSERT/RAUX2 RMSYNC TMSYNC MPUSEL AD[5] AD[6] EXCLK INSDAT 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 MCLK CS* NC DROP/RAUX1 GND TMS NC TD0 TDI TCK RST* RD* RSER TSER RCLK TCLK RS8953BEPF 2-4 Conexant VCC WR* ALE NC NC NC NC N8953BDSB RS8953B/8953SPB HDSL Channel Unit Figure 2-4. Single-Pair PQFP Pin Assignments PLLDGND SCLK MSYNC(1) PLLAGND 2.0 Pin Descriptions 2.1 Pin Assignments TLOAD1 TAUX1 PLLVCC VEXT VCC NC VCC VCC NC NC GND NC NC NC GND GND NC NC NC NC GND BCLK1 ROH1 TDAT1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VCC WR* NC NC NC NC NC NC ALE NC NC NC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 MCLK CS* NC DROP/RAUX1 GND TMS NC TDO TDI TCK RST* RD* RSER TSER RCLK TCLK RS8953SPBEPF 1 QCLK1 2 NC 3 RDAT1 4 NC 56 AD[0] AD[1] 7 AD[2] 8 AD[3] 9 AD[4] 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 INSDAT INSERT(1) INTR* RMSYNC AD[7] VCC GND TMSYNC AD[5] AD[6] EXCLK GND VCC NC MPUSEL NOTE(S): (1) These pins are only functional when RAUX_EN is not active (RAUX_EN = 0). Table 2-1. Pin Assignments (1 of 2) 80-Pin PQFP 71, 72 73 75 76 77 78 79 80 1 68-Pin PLCC 1 2 3 4 5 6 7 8 9 Signal GND BCLK2(1) TDAT2(1) RDAT2(1) GND BCLK1 ROH1 TDAT1 QCLK1 I/O GND I O I GND I O O I 80-Pin PQFP 33 35 36 37 39 40 41 43 45 68-Pin PLCC 37 38 39 40 41 42 43 44 45 Signal TDO TMS GND DROP/RAUX1 CS* MCLK VCC VCC VEXT I/O O I GND O I I VCC VCC I N8953BDSB Conexant 2-5 2.0 Pin Descriptions 2.1 Pin Assignments RS8953B/8953SPB HDSL Channel Unit Table 2-1. Pin Assignments (2 of 2) 80-Pin PQFP 3 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21, 22 23 24 25 26 27 28 29 30 68-Pin PLCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal RDAT1 AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] VCC EXCLK INSDAT INSERT/RAUX2(2) INTR* TMSYNC RMSYNC GND VCC MPUSEL TCLK RCLK TSER RSER RD* RST* I/O I I/O I/O I/O I/O I/O I/O I/O I/O VCC I I O O I O GND VCC I I O I O I I 80-Pin PQFP 32 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 65 66 67 68 69 70 2, 4, 14, 34, 38, 42, 44, 61, 62, 74 -- 68-Pin PLCC 36 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 -- Signal TDI PLLAGND PLLDGND PLLVCC VCC(SCAN_MD) ALE WR* TLOAD1 TLOAD2(1) TLOAD3(1) TAUX1 TAUX2(1) TAUX3(1) MSYNC/RAUX3(2) SCLK TDAT3(1) VCC ROH3(1) RDAT3(1) BCLK3(1) GND(SCAN_EN) QCLK3(1) ROH2(1) QCLK2(1) NC I/O I GND GND VCC VCC I I O O O I I I O O O VCC O I I GND I O I -- 31 NOTE(S): (1) (2) 35 TCK I -- -- -- These pins do not perform the functions in RS8953SPBEPF and RS8953SPBEPJ. These pins are only functional in RS8953SPBEPF and RS8953SPBEPJ when RAUX_EN is not active (RAUX_EN = 0). 2-6 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 2.0 Pin Descriptions 2.2 Signal Definitions 2.2 Signal Definitions Table 2-2. Signal Definitions (1 of 4) Signal Name I/O Microprocessor (MPU) Interface MPUSEL MPU Select I(1) Determines the type of MPU bus control signals expected during data transfers. Intel (MPUSEL = 0) or Motorola (MPUSEL = 1) bus types are supported. RD* and WR* signal functions are affected. Eight multiplexed address and data signals. The address is latched on the falling edge of ALE and selects one of 256 internal register locations (0x00-0xFF). The data bus transfers the contents of the latched address location during the read or write cycle. Active-low input enables MPU read and write cycles. The rising edge of CS* completes the read or write data transfer cycle and places the address/data bus (AD[0]-AD[7]) in a high impedance state. Active-high input enables the address bus. The falling edge of ALE latches the address internally. Signal function determined by MPUSEL: MPUSEL = 0; RD* is an active low data strobe for read cycles. MPUSEL = 1; RD* is an active low data strobe for read/write cycles. Signal function determined by MPUSEL: MPUSEL = 0; WR* is an active low data strobe for write cycles. MPUSEL = 1; WR* controls the data bus transfer direction: high during read cycles and low during write cycles. Active low, open-drain output indicates when any one or more Interrupt Request Register (IRR) bit is high and its respective Interrupt Mask Register (IMR) bit is low. INTR* remains active until all pending interrupts are cleared by writing 0s to their corresponding Interrupt Clear Register (ICR) bits. Active low input required to initialize internal circuits after power and master clock have been applied. All MPU registers remain accessible while reset is active. Unless stated otherwise, reset activation does not affect the MPU register contents. RS8953B reset activation disables interrupts on the INTR* output by forcing all 1s in the Interrupt Mask Register (IMR), and zeros in the TX_ERR_EN, DPLL_ERR_EN, and RX_ERR_EN bits. RS8953B reset activation disables auxiliary channels by forcing zeros in all TAUX_EN and RAUX_EN bits. To facilitate system upgrades from prototype Bt8953EPF, RS8953B reset activation also forces zeros in those command register bits which do not exist on Bt8953EPF, but were added on RS8953B. Description AD[0:7] Address/Data Bus I/O(1) CS* Chip Select I(1) ALE RD* Address Latch Enable Read Strobe I(1) I(1) WR* Write Strobe I(1) INTR* Interrupt Request O RST* Reset I(1) N8953BDSB Conexant 2-7 2.0 Pin Descriptions 2.2 Signal Definitions RS8953B/8953SPB HDSL Channel Unit Table 2-2. Signal Definitions (2 of 4) Signal Name I/O HDSL Channels BCLK1 BCLK2(3) BCLK3(3) QCLK1 QCLK2(3) QCLK3(3) TDAT1 TDAT2(3) TDAT3(3) TAUX1 TAUX2(3) TAUX3(3) RDAT1 RDAT2(3) RDAT3(3) RAUX1 RAUX2(3) RAUX3(3) TLOAD1 TLOAD2(3) TLOAD3(3) ROH1 ROH2(3) ROH3(3) Receive Overhead Indicator O Transmit Load Indicator O Receive Auxiliary Data O Receives data from the HDSL descrambler output on the rising edge of BCLKn. Includes all SYNC, STUFF, HOH, payload, and Z-bits. RAUXn shares pin locations with DROP, INSERT, and MSYNC, as controlled by RAUX_EN (CMD_6; addr 0xF3). Active-high output that indicates when specific payload or Z-bits are sampled at TAUXn. TLOADn is active for 8 bits coincident with each marked payload byte or 1 bit for Z-bits. The last 40 Z-bits or any combination of payload bytes may be marked. Indicate when overhead is received. Has two modes of operation: * RAS = 0. ROHn is high to mark only data passed into the RFIFO. * RAS=1. ROHn is high to mark only the last 40 Z-bits. Receive Data I(1) Transmit Auxiliary Data I(1) HDSL transmit auxiliary data input sampled on the falling edge of BCLKn when TLOADn is active. TAUXn replaces data normally supplied by PCM or HDSL transmitters to the HDSL scrambler input. Payload bytes or Z-bits can be mapped from TAUXn. HDSL receive data input sampled on the falling edge of BCLKn. The serially encoded 2B1Q sign bit is sampled when QCLKn is low, and the 2B1Q magnitude bit is sampled when QCLKn is high. Transmit Data O HDSL transmit data output at the bit rate on the rising edge of BCLKn. Serially encoded with the 2B1Q sign bit aligned to the QCLKn low level and the 2B1Q magnitude bit aligned to the QCLKn high level. Quaternary Clock I(1) Operates at the 2B1Q symbol rate (half-bit rate) and identifies sign and magnitude alignment of both RDATn and TDATn serially encoded bit streams. The falling edge of BCLKn samples QCLKn: 0 = sign bit; 1 = magnitude bit. Bit Clock I(1) Corresponds to three HDSL and three Auxiliary channels. BCLKn operates at twice the 2B1Q symbol rate. The rising edge of BCLKn outputs TDATn, TLOADn, RAUXn and ROHn; the falling edge samples QCLKn, RDATn, and TAUXn inputs. Description 2-8 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Table 2-2. Signal Definitions (3 of 4) Signal Name I/O PCM Channel TCLK Transmit Clock I(2) 2.0 Pin Descriptions 2.2 Signal Definitions Description Operates at the PCM bit rate and samples the PCM transmit inputs: TSER, TMSYNC, and INSDAT; and clocks the PCM transmit output, INSERT. Falling edge samples and rising edge outputs are normal, inverted TCLK edges are selectable. Optionally, RCLK or EXCLK can be programmed as the PCM transmit clock for loopback or externally timed applications. Operates at the PCM bit rate and clocks the PCM receive outputs: RSER, RMSYNC, and DROP. Normally, RCLK is supplied by the internal clock recovery DPLL. Optionally, EXCLK or TCLK can be programmed as the receive source during loopback or externally timed applications. Rising-edge (normal) or falling-edge (inverted) output transitions are selectable. Optionally sources the PCM Receive Clock (RCLK), or both RCLK and PCM Transmit Clock (TCLK) for systems that supply a local master clock. Normal or inverted edges are also selectable. Accepts up to 64 timeslots (1 timeslot = 8 bits) of data and an optional framing bit per PCM frame. TSER data and F-bits are then routed and mapped into the HDSL transmit channel payload. Outputs up to 64 timeslots of data and an optional F-bit per PCM frame. Receive serial data and F-bits are constructed by mapping and combining payload from the HDSL receive channels. Active-high input resets the PCM transmit time base during framed applications. TMSYNC is ignored in unframed or asynchronously mapped applications. The low to high input state transition is detected and internally delayed by a programmable bit and frame offset to coincide with the TSER and INSDAT sample location of bit 0, frame 0. The programmable sample point accommodates any system's rising edge frame or multiframe sync signal. Active-high output from the receive timebase, typically programmed to mark PCM multiframe boundaries during framed applications, and remains unused during unframed or asynchronously mapped applications. RMSYNC pulses high for one RCLK coincident with RSER output of bit 0, frame 0. Bit 0 is the first bit in TS0 of an E1 or Nx64 frame, or the F-bit of a T1 frame. Programmable bit and frame delays allow RMSYNC to mark any desired RSER bit. Active-high output pulses high for one TCLK to mark two clock cycles before the TSER and INSDAT sample point of bit 0, frame 0, of a transmit multiframe. MSYNC references the TMSYNC applied by the system or supplies the system with a master PCM frame/multiframe sync signal. RCLK Receive Clock O EXCLK External Clock I(2) TSER Transmit Serial Data Receive Serial Data Transmit Multiframe Sync I(1) RSER O TMSYNC I(1) RMSYNC Receive Multiframe Sync O MSYNC Transmit Master Sync O N8953BDSB Conexant 2-9 2.0 Pin Descriptions 2.2 Signal Definitions RS8953B/8953SPB HDSL Channel Unit Table 2-2. Signal Definitions (4 of 4) Signal Name I/O Drop/Insert DROP Drop Indicator O Active-high output indicates when specific PCM timeslots are present on RSER. DROP is high for 8 bits coincident with each marked timeslot, or 1 bit when marking F-bits. Any combination of timeslots and F-bits within the PCM frame can be marked. Alternate source of PCM transmit serial data. INSDAT is sampled by TCLK and replaces TSER when INSERT is active. INSDAT and TSER use the same frame format. INSDAT can be programmed to replace TSER data on a per-timeslot-basis. Active-high output indicates when specific INSDAT timeslots are sampled. INSERT is high for 8 bits coincident with each marked timeslot or for 1 bit when marking F-bits. Any combination of timeslots and F-bits within the PCM frame can be marked. Description INSDAT Insert Data I(1) INSERT Insert Indicator O DPLL and Power MCLK Master Clock I Runs through a multiplier PLL to create an internal 60-80 MHz reference clock for the DPLL. The 16 times symbol rate clock from a Conexant HDSL transceiver typically connects to MCLK. However, MCLK is not required to be synchronized to any HDSL or PCM channel. The DPLL reference clock is used to synthesize the PCM Recovered Clock (RCLK) based on DPLL programmed values. Optionally, a 60-80 MHz clock can be input directly on MCLK. The internal 60-80 MHz DPLL reference clock is divided by 4 to create a 15-20 MHz system clock output on SCLK. SCLK can be applied to other devices requiring a system clock (i.e., Bt8360 or Bt8510). Used to bias input protection diodes. If interfacing to 5 V powered devices, connect this pin to 5 V. Otherwise, connect 3.3 V to this pin. 3.3 Vdc +/- 0.3 V power input for the PLL. 0 Vdc ground reference for the PLL. 0 Vdc analog ground reference for the PLL. Tied to GND unless PLL operation is desired above 80 MHz. 3.3 Vdc +/- 0.3 V power input. 0 Vdc ground reference. Boundary scan clock samples and outputs test access signals. Active-high enables test access port. Sampled by TCK rising edge. Serial data for boundary scan chain. Sampled by TCK rising edge. Outputs serial data from boundary scan chain on TCK falling edge. SCLK System Clock O VEXT PLLVCC PLLDGND PLLAGND VCC GND TCK TMS TDI TDO NOTE(S): (1) (2) External Voltage PLL Power PLL Ground PLL Analog Ground Power Ground Test Clock Test Mode Select Test Data Input Test Data Output I I I I I I I I(1) I(1) O Internal pull-ups (80-100 kW) are present on inputs to allow unused inputs to remain disconnected. Internal pull-downs (80-100 kW) are present on inputs to allow unused inputs to remain disconnected. (3) The pins do not perform these functions in RS8953SPBEPF and RS8953SPBEPJ. 2-10 Conexant N8953BDSB 3 3.0 Circuit Descriptions 3.1 MPU Interface The Microprocessor Unit (MPU) interface consists of an 8-bit parallel multiplexed address-data bus, an associated bus control signal, and a maskable interrupt request output, as illustrated in Figure 3-1 and Figure 3-2. The MPU interface is compatible with 8-bit processors running at bus cycle speeds up to 16 MHz. Systems that use 16 or 32-bit processors can add an external address buffer and data transceiver to connect the RS8953B. Faster bus speeds require external wait-state insertion logic. Figure 3-1. MPU Bus Control Logic ALE AD[7:0] MPUSEL Address To Registers From Registers RD* Read Strobe WR* Write Strobe CS* N8953BDSB Conexant 3-1 3.0 Circuit Descriptions 3.1 MPU Interface RS8953B/8953SPB HDSL Channel Unit Figure 3-2. MPU Interrupt Logic Read IMR DATA Mask INTR* Write IMR Read IRR Interrupt Event Set Request Other Interrupt Sources Reset Write ICR 3.1.1 Address/Data Bus Address/data bus pins AD[7:0] allow MPU access to RS8953B internal registers. Read and write access is allowed at any of the 256 address locations, but only defined register address locations are applicable (see Table 4-1). 3.1.2 Bus Controls Five signals control register access: ALE, CS*, RD*, WR*, and MPUSEL. The address on AD[7:0] is latched on the falling edge of ALE, and CS* is an active-low port enable for all read and write operations. If CS* is high, the MPU port is inactive. Different styles of bus control are supported using separate read and write strobes for Intel-style buses, or common data strobe with a combined read/write signal for Motorola-style buses. When MPUSEL = 0 (Intel bus), RD* is an active-low read enable and WR* is an active-low write strobe. While RD* and CS* are low, the addressed register's data is driven onto AD[7:0]. If WR* and CS* are low, the rising edge of WR* or CS* latches data from AD[7:0] into the register. When MPUSEL = 1 (Motorola bus), RD* is an active-low data strobe for both read and write cycles, and WR* is a read/write select. While RD* and CS* are low and WR* is high, the addressed register's data is driven onto AD[7:0]. If RD*, CS*, and WR* are low, the rising edge of RD*, CS*, or WR* latches data from AD[7:0]. 3-2 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.1 MPU Interface 3.1.3 Interrupt Request The open-drain interrupt request output (INTR*) indicates when a particular set of transmit, receive, or common status registers have been updated. Eight maskable interrupt sources are requested on the common INTR* pin: 1. 2. 3. 4. 5. 6. 7. 8. TX1 = Channel 1 Transmit 6 ms Frame TX2 = Channel 2 Transmit 6 ms Frame TX3 = Channel 3 Transmit 6 ms Frame RX1 = Channel 1 Receive 6 ms Frame RX2 = Channel 2 Receive 6 ms Frame RX3 = Channel 3 Receive 6 ms Frame TX_ERR = Logical OR of 3 Transmit Channel Errors RX_ERR = Logical OR of 3 Receive Channel Errors and DPLL Errors All interrupt events are edge-sensitive and synchronized to their respective HDSL channel's 6 ms frame. The basic structure of each interrupt source is shown in Figure 3-2, with three associated registers: Interrupt Mask Register [IMR; addr 0xEB], where writing a 1 to an IMR bit prevents the associated interrupt source from activating INTR*; Interrupt Request Register [IRR; addr 0x1F], where active interrupt events are indicated by IRR bits that are read high; and Interrupt Clear Register [ICR; addr 0xEC], where writing a 0 to an ICR bit clears the associated IRR bit, and if no other interrupts are pending, deactivates INTR*. Error interrupts (TX_ERR and RX_ERR) are combined from multiple sources, each source having its own interrupt enable. Individual errors are reported in the common Error Status Register [ERR_STATUS; addr 0x3C] which is cleared by an MPU read. 3.1.4 Hardware Reset Assertion of hardware reset (RST*) is required to preset all IMR bits, clear all error interrupt enables, and thus disable INTR* output. For backward compatibility with Bt8953 software, RST* also clears the command register bits added to RS8953B which aren't present on prototype Bt8953. All other registers are MPU accessible while RST* is asserted. N8953BDSB Conexant 3-3 3.0 Circuit Descriptions 3.2 PCM Channel RS8953B/8953SPB HDSL Channel Unit 3.2 PCM Channel The Pulse Code Multiplexed (PCM) channel displayed in Figure 3-3 consists of independent transmit and receive formatter circuits to control the flow of serial data between PCM and HDSL channels, to establish alignment between PCM and HDSL frames, and maintain synchronization between PCM and HDSL clocks. Framed serial data consists of a variable number of multiplexed 8-bit timeslots, plus an optional framing bit (F-bit), a variable number of PCM frames repeated to form a PCM multiframe, and a variable number of multiframes concatenated to form a PCM 6 ms frame. T1, E1, or custom Nx64 frame formats are selected by programming the PCM Formatter Registers (see Table 4-4) to define the number of bits per frame [FRAME_LEN; addr 0xC8], frames per multiframe [MF_LEN; addr 0xC6], and multiframes per 6 ms frame [MF_CNT; addr 0xC7]. Unframed serial data is selected in the same manner; however, the number of bits per frame act as a single channel rather than individual timeslots and can support PCM frame lengths that are not integer multiples of 8-bits. In framed or unframed applications, PCM timebases create a 6 ms frame period based on the Transmit Clock (TCLK) and Receive Clock (RCLK). PCM timebases are programmed to equal approximately the HDSL 6 ms frame period defined by the HDSL Frame Length [HFRAME_LEN; addr 0xCA] in relation to the master HDSL channel's Bit Clock (BCLKn). The resultant PCM and HDSL 6 ms frame intervals are used to establish alignment between PCM and HDSL frames, to maintain synchronization between transmit clocks by performing bit stuffing, and to recover PCM receive clock by comparing phase offset between frames. Figure 3-3. PCM Channel Block Diagram TMSYNC MSYNC TSER INSDAT INSERT TCLK CH1 Transmit (Data and Sync) CH2 Transmit Transmit Formatter CH3 Transmit PCM 6 ms Sync Loopback (Data and Sync) RMSYNC RSER DROP EXCLK RCLK CH1 Receive (Data and Sync) Receive Formatter CH2 Receive CH3 Receive Recovered Clock DPLL Master Sync 3-4 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.2 PCM Channel 3.2.1 PCM Transmit The PCM transmit formatter shown in Figure 3-4 accepts framed or unframed serial data on the TSER and INSDAT inputs. Both inputs are sampled on the clock edge selected by TCLK_SEL [CMD_2; addr 0xE6] according to the format of the PCM Multiframe Sync (MSYNC) output. The PCM transmit timebase outputs MSYNC to mark two clock cycles before the PCM input sample point of bit 0, frame 0. The timebase either references the system's Transmit Multiframe Sync (TMSYNC) input or supplies MSYNC without regard to TMSYNC, as controlled by the PCM_FLOAT setting [CMD_2; addr 0xE6]. Figure 3-4. PCM Transmit Block Diagram TSER RSER Previous INSDAT PRBS HP_LOOP INSERT MSYNC TMSYNC Bit Delay PCM Transmit Timebase RMSYNC TCLK PCM_FLOAT RCLK TCLK_SEL Frame Length MF Length Routing Table TFIFO 1 TFIFO 2 TFIFO 3 TFIFO_WL 1 TFIFO_WL 2 TFIFO_WL 3 CH1 DATA CH2 DATA CH3 DATA CH1 TSYNC CH2 TSYNC CH3 TSYNC TFIFO_RST Frame Delay MF Count PCM 6 MS PCM TCLK = Command Register Bit The MSYNC leads the sampling of bit 0, frame 0, on TSER and INSDAT by two TCLK bit positions. If PCM_FLOAT is active, the transmit timebase ignores TMSYNC and outputs MSYNC according to the PCM formatter register values: FRAME_LEN, MF_LEN, and MF_CNT. In this case, MSYNC acts as PCM bus master and supplies a multiframe sync reference to the system as illustrated in Figure 3-5, but without a specific TMSYNC relationship. If PCM_FLOAT is inactive, MSYNC is aligned to TMSYNC (as shown in Figures 3-5 and 3-6). The system locates the sampling point of bit 0, frame 0, with respect to TMSYNC by programming the number of bit delays [TFRAME_LOC; addr 0xC0] from TMSYNC's rising edge to bit 0 of the PCM frame. In addition, it locates the frame 0 input sample point by programming the additional number of frame delays [TMF_LOC; addr 0xC2] needed to mark the first frame of a PCM multiframe. N8953BDSB Conexant 3-5 3.0 Circuit Descriptions 3.2 PCM Channel RS8953B/8953SPB HDSL Channel Unit Figure 3-5 shows the phase relationship between TMSYNC and MSYNC when TFRAME_LOC is equal to 0. Figure 3-6 illustrates the progression of MSYNC with increasing bit and frame delays. NOTE: MSYNC can optionally mark the start of every PCM frame (bit 0, all frames) by setting MF_LEN equal to 1 frame per multiframe. Figure 3-5. PCM Transmit Sync Timing TCLK TMSYNC TFRAME_LOC=0, TMF_LOC=0 MSYNC FRAME_LEN[X] TSER INSDAT 0 1 2 X Sample PCM Bit 0 or F-bit, of Frame 0 NOTE(S): TCLK falling edge samples and rising edge outputs shown per TCLK_SEL = 00 Figure 3-6. PCM Transmit Data Timing TMSYNC 0 1M TFRAME_LOC[M] = MSYNC Bit Delay 01N MSYNC FRAME_LEN[X] = PCM Frame Length PCM Bit PCM Frame PCM Mframe 0 X MF_LEN[Y] = PCM Multiframe Length Frame 0 Frame Y MF_CNT[Z] = Mframes per 6 ms period Mframe 0 Mframe 1 Mframe Z TMF_LOC[N] = MSYNC Frame Delay 3.2.1.1 Transmit Synchronization Alignment of transmit PCM data in relation to MSYNC determines whether PCM and HDSL frames are synchronously mapped. The RS8953B does not examine transmit data for T1, E1, or application framing patterns. Therefore, the system must apply PCM data aligned to MSYNC when synchronous mapping is desired. If the system applies PCM bit 0, frame 0 coincident with MSYNC, then the transmit router guarantees that each PCM timeslot placed in the TFIFO will be aligned and mapped into a specific HDSL payload byte. In addition, timeslots from the first PCM frame are mapped to payload bytes in the first HDSL payload block, and the start of a PCM multiframe is aligned with the start of an HDSL frame. 3-6 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.2 PCM Channel If the system does not apply PCM data aligned to MSYNC, then the application is asynchronously mapped, and the placement of timeslots, frames and multiframes is not aligned to HDSL payload bytes, blocks, or frames. Asynchronously mapped applications require the entire PCM serial data stream be transported; the transmitter cannot discern timeslot or frame boundaries. Synchronous mapping allows selective timeslot routing to HDSL channels, thus enabling transport to multiple remote sites and allowing PCM to operate at rates which exceed available HDSL payload. However, synchronously mapped channels are subject to changes in transmit frame alignment, resulting from changes of the TMSYNC reference. ETSI defines synchronous and asynchronous mapping depending on the type of E1 transport. Bellcore requires synchronous T1 frame mapping for F-bits to align with Z-bit positions. (Refer to frame formats and mapping arrangements illustrated in Figures 3-16 through 3-18, and Tables 3-2 and 3-3). 3.2.1.2 Transmit Routing Table Timeslot and F-bit data are shifted from PCM inputs into the TFIFO according to the programmed transmit Routing Table [ROUTE_TBL; addr 0xED] assignments. The routing table contains an entry for each PCM timeslot and the system selects 1, 2, 3, or none of the HDSL transmit channels as the timeslot's destination. The system also selects which source (TSER, INSDAT, PRBS generator or previous timeslot) supplies data for the destination. In this manner, the routing table allows a single timeslot to be routed to more than one HDSL channel, and a single timeslot to supply a repeated value to destination channels. If INSDAT supplies source data, then the INSERT output marks PCM sampling times corresponding to that timeslot (refer to Figure 3-7 for INSERT signal timing). Note that INSDAT is sampled through the previous buffer and is routed in the subsequent timeslot table entry. Incoming PCM transmit timeslots can be replaced by a test pattern on a per-timeslot basis, or the entire framed or unframed PCM transmit channel can be replaced by a test pattern (see PRBS_MODE in CMD_3; addr 0xE7 and BER_SEL in CMD_6; addr 0xF3). When test pattern is enabled on a per-timeslot basis according to the programmed transmit routing table assignments, the PRBS generator is only clocked during enabled timeslots and may output a single test pattern sequence over multiple discontinuous timeslots. The test pattern is selected from one of four Pseudo-Random Bit Sequence (PRBS) patterns or a programmable 8-bit fixed pattern [FILL_PATT; addr 0xEA]. PRBS pattern selections are: 24-1, 215-1, 223-1 and Quasi-Random Signal Sequence (QRSS), where QRSS equals 220-1 PRBS with 14-zero limit. The 215-1 test pattern has an inverter in the data path. RS8953B does not provide a mechanism to automatically insert logic errors in the test pattern, although the capability to synchronize and measure test pattern errors is provided by the BER meter. 3.2.1.3 PRBS Generator N8953BDSB Conexant 3-7 3.0 Circuit Descriptions 3.2 PCM Channel RS8953B/8953SPB HDSL Channel Unit 3.2.1.4 Drop/Insert Channel PCM channels can carry timeslot data along a backplane that serves multiple interfaces or subscriber line cards (see Figure 1-3) which requires that each interface or line card be able to drop or insert individual PCM timeslots. The RS8953B provides DROP and INSERT signals to facilitate external multiplexing of individual timeslots from a shared PCM backplane, but does not provide the capability to three-state its data outputs during specific PCM timeslots. DROP and INSERT signals are programmed to mark RSER data output and INSDAT data input timeslots via the receive Combination Table [COMBINE_TBL; addr 0xEE] and the transmit Routing Table [ROUTE_TBL; addr 0xED] assignments. NOTE: Only INSDAT provides an alternate source for each PCM transmit timeslot and does not expand the total number of available timeslots. Figure 3-7 shows DROP and INSERT timing as it relates to PCM bus timing during T1/E1 applications. Figure 3-7. Drop/Insert Channel Timing Receive RCLK Transmit TCLK RMSYNC TMSYNC TSER INSDAT RSER 0 1 2 3 4 5 6 7 8 9 Timeslot 0 DROP INSERT TSER INSDAT RSER F 1 2 3 4 5 6 7 8 9 Timeslot 0 DROP INSERT } } (E1_MODE = 1) (E1_MODE = 0) NOTE(S): 1. 2. 3. 4. Falling-edge samples and rising-edge outputs shown per TCLK_SEL = 00 and RCLK_SEL = 00. First entry of Transmit ROUTE_TBL [addr 0xED] shown programmed with INSERT_EN = 1. First entry of Receive COMBINE_TBL [addr 0xEE] shown programmed with DROP_EN = 1. For illustrative purposes only, Transmit and Receive are shown phase, frequency, and frame aligned. 3-8 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.2 PCM Channel 3.2.1.5 TFIFO Water Levels Each HDSL transmit channel aligns the start of its output frame with respect to the PCM 6 ms sync according to the programmed TFIFO water level values [TFIFO_WL; addr 0x05]. PCM 6 ms sync is created from MSYNC by the divisor programmed in MF_CNT [addr 0xC7]. The HDSL 6 ms frame is created from PCM 6 ms by adding the TFIFO_WL phase offset programmed for each channel, as shown in Figure 3-8. In this manner, HDSL output frames are slaved to PCM frame timing regardless of whether the system chooses to synchronize PCM data to MSYNC. The phase offset between PCM and HDSL 6 ms frames is programmed by TFIFO_WL as the number of TCLK cycle delays from the start of PCM 6 ms sync to the start of HDSL 6 ms frame. Thus, this phase offset determines the amount of PCM data written to the TFIFO before the HDSL transmitter begins extracting data from the TFIFO, which also defines each transmitter's data throughput delay and subsequently the differential delay with respect to other HDSL channels. The actual phase offset varies over time as a result of stuff bit insertion as well as PCM and HDSL clock jitter and wander. Therefore, TFIFO_WL is only used to establish the initial phase offset between PCM and HDSL frames when the MPU issues the TFIFO_RST [addr 0x0D] command, or after a stuffing error. Because all or part of the PCM frame can be routed to each HDSL channel, the system must consider transmit routing table assignments and other data path delays when programming TFIFO_WL values. Sufficient phase offset must be established to allow time for the first programmed timeslot to be routed from the PCM frame into the TFIFO, to absorb the phase offset created by HDSL overhead, to stuff bit insertion and clock frequency variation, and to unload the first timeslot from the TFIFO and map data into the HDSL payload byte. Conversely, to avoid TFIFO overflow, phase offset must be limited so the amount of data residing in the TFIFO does not exceed the number of PCM bits routed during one PCM frame, the maximum TFIFO depth (186 bits), or the total HDSL payload block length [HFRAME_LEN; addr 0xCA]. Figure 3-8. TFIFO Water Level Timing Differential Delay MSYNC PCM (Bit) 0 1 2 3 4 5 6 7 8 9 10 X CH1; TFIFO_WL[X] HDSL (CH1) CH2; TFIFO_WL[Y] HDSL (CH2) Y Z 16-bit SYNC + HOH Z byte1 from TFIFO1 byte2 16-bit SYNC + HOH Z byte1 from TFIFO2 byte2 CH3; TFIFO_WL[Z] HDSL (CH3) 16-bit SYNC + HOH Z byte1 from TFIFO3 NOTE(S): 1. PCM and HDSL shown synchronously mapped (PCM_FLOAT = 0). 2. Equal TFIFO_WL settings provide minimum differential delay. N8953BDSB Conexant 3-9 3.0 Circuit Descriptions 3.2 PCM Channel RS8953B/8953SPB HDSL Channel Unit 3.2.2 PCM Receive The PCM receive formatter shown in Figure 3-9 constructs the serial data (RSER) output according to receive combination table settings and the frame format defined by the PCM Formatter Registers (see Table 4-4). The PCM receiver operates on the clock edge selected by RCLK_SEL [CMD_2; addr 0xE6] and references the PCM receive timebase and RSER frame location to the alignment provided by the master HDSL channel's receive 6 ms frame. Therefore, the position of bit 0, frame 0 output on RSER, is slaved to the HDSL receiver selected as master by MASTER_SEL [CMD_5; addr 0xE9]. The RSER timing relationship with respect to PCM 6 ms sync is shown in Figure 3-10. PCM 6 ms sync is created from the HDSL 6 ms frame delayed by the programmed RFIFO_WL [addr 0xCD] value, as shown in Figure 3-13. Figure 3-9. PCM Receive Block Diagram BER_SEL DBANK 1 BER Meter TSER DBANK 2 DBANK 3 RSER SIG Table RFIFO 1 RFIFO 2 PP_LOOP RFIFO 3 Combine Table TMSYNC RMSYNC Frame Delay PCM Receive Timebase Bit Delay MF Length Frame Length MF Count RFIFO_WL CH1 RSYNC CH2 RSYNC CH3 RSYNC DPLL RCLK EXCLK TCLK = Command Register Bit RCLK_INV RCLK_SEL FROM CH1 RMAP FROM CH2 RMAP FROM CH3 RMAP DROP RX_RST MASTER_SEL RCLK 3-10 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Figure 3-10. PCM Receive Data Timing HDSL 6ms Master RFIFO_WL = PCM Bit Delay PCM 6ms 1 23M RFRAME_LOC[M] = RMSYNC Bit Delay 123456N RMSYNC FRAME_LEN[X] = PCM Frame Length RSER Bit RSER Frame RSER Mframe 0 X MF_LEN[Y] = PCM Multiframe Length Frame 0 Frame Y MF_CNT[Z] = PCM Mframes per 6 ms period Mframe 0 RMF_LOC[N] = RMSYNC Frame Delay 3.0 Circuit Descriptions 3.2 PCM Channel Mframe Z NOTE(S): RMSYNC can mark any RSER bit position by programming RFAME_LOC and RMF_LOC. N8953BDSB Conexant 3-11 3.0 Circuit Descriptions 3.2 PCM Channel RS8953B/8953SPB HDSL Channel Unit 3.2.2.1 Receive Synchronization The Receive Multiframe Sync (RMSYNC) output can be programmed to mark any bit position within the receive multiframe and does not affect RSER alignment with respect to the PCM 6 ms frame. Figure 3-11 shows the phase offset between PCM 6 ms sync and RMSYNC for various bit and frame delay values [RFRAME_LOC and RMF_LOC; addr 0xC3-C5]. The RS8953B does not search receive data for T1, E1, or other specific framing patterns and must always infer PCM receive frame timing from the master HDSL channel's RSYNC reference. When transmit PCM frames are synchronously mapped, the system can program fixed receive delay values for RFRAME_LOC and RMF_LOC so that RMSYNC marks the desired RSER bit position. For unframed or asynchronously mapped applications, the RMSYNC output can be ignored, or the remote system can measure transmit phase offset and communicate the necessary phase displacement to the central site. Figure 3-11. PCM Receive Sync Timing PCM 6ms RSER Bit 0, Frame 0 RSER 0 1 2 3 4 RFRAME_LOC = 1, RMF_LOC = 0 RMSYNC 0 1 RSER Bit 0, Frame 1 2 3 4 RMSYNC RFRAME_LOC = 2, RMF_LOC = 0 RMSYNC RFRAME_LOC = 5, RMF_LOC = 0 RFRAME_LOC = 1, RMF_LOC = 1 RMSYNC RMSYNC RFRAME_LOC = 2, RMF_LOC = 1 RMSYNC RFRAME_LOC = 5, RMF_LOC = 1 3.2.2.2 Receive Combination Table RSER data output for each PCM timeslot is supplied from one of seven data sources via programmed assignments in the receive Combination Table [COMBINE_TBL; addr 0xEE]. RSER can be supplied by payload bytes from one of three HDSL receive channels, from fixed 8-bit patterns from one of three Data Bank Registers [DBANK1-3; addr DC-DE] or from groomed Channel Associated Signaling (CAS) from the Receive Signaling Table [RSIG_TBL; addr 0xF2]. The receive combination table contains up to 64 table entries corresponding to RSER timeslot destinations and each table entry selects one of seven data sources. The first PCM timeslot destination (counting from timeslot 0) that selects a particular HDSL channel's payload byte receives the first payload byte mapped into the RFIFO from that particular HDSL channel's payload block, regardless of whether PCM is synchronously mapped. Asynchronously mapped data is reconstructed into a serial PCM bit stream which maintains bit sequence integrity, provided that the entire PCM channel is formed from combined payload bytes. Each receive combination table entry also selects whether the associated data is copied to the BER meter for test pattern examination. 3-12 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.2 PCM Channel 3.2.2.3 BER Meter PCM timeslots from TSER or RSER can be examined for test patterns on a per timeslot-basis, or the entire framed or unframed PCM channel from TSER can be examined (see PRBS_MODE in CMD_3; addr 0xE7 and BER_SEL in CMD_6; addr 0xF3). When a test pattern is examined on a per timeslot-basis from receive combination or transmit routing table assignments, the BER meter is only clocked during enabled timeslots and expects a single test pattern to arrive in one sequence from all enabled timeslots. The expected test pattern is selected from one of four Pseudo-Random Bit Sequence (PRBS) patterns or a programmable 8-bit fixed pattern [FILL_PATT; addr 0xEA]. PRBS pattern selections are: 24-1, 215-1, 223-1 and Quasi-Random Signal Sequence (QRSS), where QRSS equals 220-1 PRBS with 14-zero limit. The MPU configures BER_SCALE [CMD_3; addr 0xE7] to determine the test measurement interval from a range of 221-231 bit lengths, starts BER measurement by issuing BER_RST [addr 0xEF], then monitors test results [BER_METER; addr 0x1D] and test status [BER_STATUS; addr 0x1E]. Figure 3-12. PRBS/BER Measurements BER_SEL = NORMAL BER_SEL = PCM SERIAL BER_SEL = PCM FRAMED PCM HDSL PRBS BER TSER BER ROUTE_TBL ROUTE_TBL COMBINE_TBL RSER PRBS HDSL PRBS TSER BER Test Selected HDSL Payload Test Entire PCM Channel Test Selected PCM Timeslots N8953BDSB Conexant 3-13 3.0 Circuit Descriptions 3.2 PCM Channel RS8953B/8953SPB HDSL Channel Unit 3.2.2.4 RFIFO Water Level The RFIFO Water Level [RFIFO_WL; addr 0xCD] determines the PCM and HDSL receiver's phase error tolerance and receive throughput data delay by establishing a fixed phase offset between the master HDSL channel's receive 6 ms frame and the PCM 6 ms sync, as shown in Figure 3-13. RFIFO_WL selects the number of RCLK bit delays from HDSL to PCM 6 ms frames and controls the amount of time available for the HDSL receiver to map data into the RFIFO before the PCM receiver begins extracting data from the RFIFO. Because all or part of an HDSL payload block can be mapped into a PCM frame, the system must consider Receive Payload Map [RMAP; addr 0x64], Combination Table [COMBINE_TBL; addr 0xEE] and other data path delays when programming RFIFO_WL values. Sufficient phase offset must be established to allow time for HOH, SYNC, and STUFF bit extraction (20 HDSL bits), to load one payload byte (8 HDSL bits), to unload one PCM timeslot (8 PCM bits), to account for differential transmission delay (up to 65 s) and PCM reconstruction (up to 96 PCM bits in T1 mode), and time to tolerate clock variance (1 to 8 PCM bits). Conversely, to avoid RFIFO overflow, phase offset must be limited so the amount of data residing in the RFIFO never exceeds the number of PCM bits mapped during one PCM frame, the maximum RFIFO depth (185 bits), or the total HDSL payload block length [HFRAME_LEN; addr 0xCA]. The actual phase offset between HDSL and PCM 6 ms frames varies over time as a result of STUFF bit extraction, clock variance, and differential phase delays. Therefore, RFIFO_WL is only used to establish the initial phase offset between HDSL and PCM receive frames when the MPU issues the Reset Receiver command [RX_RST; addr 0xF1]. Figure 3-13. RFIFO Water Level Timing Differential Delay RDAT1 16-bit SYNC + HOH Z1 byte1 to RFIFO1 byte2 RDAT2 16-bit SYNC + HOH Z byte1 to RFIFO2 byte2 RDAT3 16-bit SYNC + HOH Z byte1 to RFIFO3 byte2 RFIFO_WL = PCM Bit Delay PCM 6ms Internal RSER RSER Bit 0, Frame 0 NOTE(S): CH1 selected as Master HDSL channel. 01234 3-14 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.3 Clock Recovery DPLL 3.3 Clock Recovery DPLL The Digital Phase Locked Loop (DPLL) shown in Figure 3-14 synthesizes the PCM Receive Clock (RCLK) from a 60-80 MHz High Frequency Clock (HFCLK). HFCLK is developed by analog PLL multiplication of the MCLK input frequency, or HFCLK is applied directly to the MCLK input (see PLL_MUL and PLL_DIS in CMD_1; addr 0xE5). The analog PLL requires external loop filter components and connections as shown in Figure 6-1. HFCLK must be in the range of 60-80 MHz, but requires no specific frequency or phase relationship to PCM or HDSL clocks. Open or closed loop operation is selected by DPLL_NCO [CMD_5; addr E9]. Figure 3-14. DPLL Block Diagram PLL /4 ~ 15-20 MHz HFCLK ~ 60-80 MHz NCO SCLK DPLL_FACTOR / N-1 /N / N+1 /2 MCLK x PLL_MUL / PLL_DIV PLL_DIS GCLK ~ 12 MHz Phase Detector CH1 RSYNC CH2 RSYNC CH3 RSYNC MASTER_SEL DPLL_RST DPLL_NCO HDSL 6ms PCM 6ms CNT Start Stop RST DPLL Filter DPLL_GAIN RCLK /N / N+1 / N+2 SUM Z-1 Z-1 INIT DPLL_RESID OVF / MF_CNT / MF_LEN / FRAME_LEN N8953BDSB Conexant 3-15 3.0 Circuit Descriptions 3.3 Clock Recovery DPLL RS8953B/8953SPB HDSL Channel Unit In closed loop operation, the Numerical Controlled Oscillator (NCO) synthesizes the nominal RCLK frequency according to the programmed HFCLK integer scale factor [DPLL_FACTOR; addr 0xD7] and the fractional scale factor [DPLL_RESID; addr 0xD5]. The NCO locks the RCLK frequency to the HDSL reference by varying the RCLK phase based on the filtered phase error from the DPLL filter and the DPLL phase detector. Phase error is the phase difference measured from the receive PCM 6 ms sync to the master HDSL channel's 6 ms frame. Phase error is quantized in units of GCLK, where GCLK is set to approximately 12 MHz the from division of HFCLK by the programmed value of PLL_DIV [CMD_1; addr 0xE5]. The phase detector measures and reports the Phase Error [PHS_ERR; addr 0x38] coincident with the master HDSL channel's receive 6 ms frame interrupt. The phase detector automatically reinitializes, if phase error exceeds 511 GCLK cycles according to the initialization mode selected by PHD_MODE [CMD_7; addr 0xF4]. The DPLL filter is a Type II digital filter in which the gain [DPLL_GAIN; addr 0xD8] determines the closed loop DPLL filter bandwidth. During open loop operation, the NCO synthesizes the RCLK frequency according to the programmed HFCLK integer and fractional scale factors, but ignores phase detector error outputs. In this case, RCLK frequency accuracy is dependent on HFCLK accuracy ( 20 ppm) and programmed scale factor accuracy (~ 2 Hz). Open loop operation is useful during remote HTU applications to provide a stable RCLK output frequency while HDSL channels are performing startup activities. 3-16 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.4 Loopbacks 3.4 Loopbacks The RS8953B provides multiple PCM and HDSL loopbacks, as shown in Figure 3-15. The output towards which data is looped is called the test direction. Loopback activation in the test direction does not disrupt the through data path in the non-test direction. Data path options (refer to Table 4-7) are provided to replace data in the non-test direction with fixed or PRBS test patterns. Table 3-1 shows the loopback controls which are designated by initials corresponding to test direction and the channel from which data is looped. PP_LOOP and HP_LOOP automatically switch both PCM data and PCM multiframe sync signals to the test direction. In these loopback modes, the PCM transmit and receive clocks are not automatically switched to the test direction. The PCM transmit and receive clocks must be properly configured for these loopback modes to operate. When performing PH_LOOP, all HDSL channels that have payload data mapped require that PH_LOOP mode be enabled to complete PCM channel loopback on the HDSL side. Also, the same tap must be used for the RS8953B scrambler and descrambler, or both the RS8953B scrambler and descrambler must be disabled. When performing HH_LOOP, the scrambler and descrambler in the HDSL transceivers must be enabled. Different tap must be used in each direction. This is required to prevent the exact same data to be sent in both directions. If the exact same data is sent in both directions, the echo canceler in the HDSL transceivers will consider the data an echo and cancel the data. Also, the same tap must be used for the RS8953B scrambler and descrambler, or both the RS8953B scrambler and descrambler must be disabled. Figure 3-15. PCM and HDSL Loopbacks PCM Channel TSER PP_LOOP RSER HDSL Channel 2 TDAT2 PH_LOOP HH_LOOP RDAT2 HDSL Channel 3 TDAT3 PH_LOOP HH_LOOP RDAT3 HP_LOOP PH_LOOP HH_LOOP RDAT1 HDSL Channel 1 TDAT1 N8953BDSB Conexant 3-17 3.0 Circuit Descriptions 3.4 Loopbacks RS8953B/8953SPB HDSL Channel Unit Table 3-1. PCM And HDSL Loopbacks Loopback PP_LOOP HP_LOOP PH_LOOP PH_LOOP PH_LOOP HH_LOOP HH_LOOP HH_LOOP Command Register CMD_2; addr 0xE6 CMD_2; addr 0xE6 RCMD_2; addr 0x61 RCMD_2; addr 0x81 RCMD_2; addr 0xA1 TCMD_2; addr 0x07 TCMD_2; addr 0x27 TCMD_2; addr 0x47 Test Direction Receive Transmit Receive Receive Receive Transmit Transmit Transmit Loopback Description PCM Loopback on PCM Side HDSL Loopback on PCM Side PCM Loopback on HDSL Channel 1 PCM Loopback on HDSL Channel 2 PCM Loopback on HDSL Channel 3 HDSL Loopback on HDSL Channel 1 HDSL Loopback on HDSL Channel 2 HDSL Loopback on HDSL Channel 3 3-18 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.5 HDSL Channel 3.5 HDSL Channel The three identical HDSL channels (CH1, CH2, and CH3) consist of separate transmit and receive circuits that are responsible for the assembly of HDSL output frames and the disassembly of HDSL receive frames. The basic structure of an HDSL frame is shown in Table 3-2. Each frame is nominally 6 ms in length and consists of 48 payload blocks with each block containing a single Z-bit, plus an application-specific number of payload bytes. The MPU selects the desired payload block length in HFRAME_LEN [addr 0xCA], in which the length is programmed to equal the number of payload and Z-bits. Groups of 12 payload blocks are concatenated and separated by an ordered set of HDSL overhead bits, in which a 14-bit SYNC word pattern identifies the starting location of the HDSL frame. 50 overhead bits are defined in one HDSL frame, but the last 4 STUFF (sq1-sq4) bits are nominally present in alternate frames. Therefore, one frame contains an average of 48 overhead bits. N8953BDSB Conexant 3-19 3.0 Circuit Descriptions 3.5 HDSL Channel RS8953B/8953SPB HDSL Channel Unit Table 3-2. HDSL Frame Structure and Overhead Bit Allocation HOH Bit # 1-14 15 16 Symbol sw1-sw14 losd febe Bit Name SYNC word Loss of Signal Far End Block Error Payload Blocks 1-12 HOH Register Bit -- IND[0] IND[1] 17-20 21-22 23 24 25 26 eoc1-eoc4 crc1-crc2 ps1 ps2 bpv eoc5 Embedded Operations Channel Cyclic Redundancy Check HTU-R Power Status Power Status Bit 2 Bipolar Violation Embedded Operations Channel Payload Blocks 13-24 EOC[0]-EOC[3] -- IND[2] IND[3] IND[4] EOC[4] 27-30 31-32 33 34 35 36 eoc6-eoc9 crc3-crc4 hrp rrbe rcbe rega Embedded Operations Channel Cyclic Redundancy Check HDSL Repeater Present Repeater Remote Block Error Repeater Central Block Error Repeater Alarm Payload Blocks 25-36 EOC[5]-EOC[8] -- IND[5] IND[6] IND[7] IND[8] 37-40 41-42 43 44 45 46 eoc10-eoc13 crc5-crc6 rta rtr uib uib Embedded Operations Channel Cyclic Redundancy Check Remote Terminal Alarm Ready to Receive Unspecified Indicator Bit Unspecified Indicator Bit Payload Blocks 37-48 EOC[9]-EOC[12] -- IND[9] IND[10] IND[11] IND[12] 47 48 49 50 sq1 sq2 sq3 sq4 Stuff Quat Sign Stuff Quat Magnitude Stuff Quat Sign Stuff Quat Magnitude STUFF[0] STUFF[1] STUFF[2] STUFF[3] 3-20 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.5 HDSL Channel In T1 framing mode [E1_MODE = 0 in CMD_1; addr 0xE5], Z-bit positions are replaced by F-bits and are treated as payload with respect to the PCM channel. Figure 3-16 shows a standard application 2T1 frame format in which each payload block contains 1 F-bit, plus 12 payload bytes. The figure also illustrates F-bits routed as payload to both HDSL channels and demonstrates the order in which PCM timeslots are routed to payload bytes: bytes 1 through 12 correspond to PCM timeslots 1-12 routed on CH1, bytes 13 through 24 correspond to PCM timeslots 13-24 routed on CH2. CH3 is unused in 2T1 application. Standard application 2E1 and 3E1 frame formats are shown in Figure 3-17 and Figure 3-18, respectively. Standard mapping of PCM data places alternating bytes in each HDSL channel, as shown by byte numbering. The 2E1 payload block contains 18 payload bytes, and the 3E1 payload block contains 12 bytes. In E1 framing mode [E1_MODE = 1 in CMD_1; addr 0xE5], 48 Z-bits are treated as overhead and are under MPU control. (Refer to Table 3-5 for Z-bit definitions). Table 3-3 shows additional examples of frame mapping options. Figure 3-16. 2T1 Frame Format 2T1 FRAME 2351 OR 2353 QUATS 7Q SS QQ 12 1Q 12 X 48.5 = 582Q 5Q B 0 2 B 1 2 HB O1 H3 B 1 4 582Q B 2 4 5Q HB O2 H5 B 2 6 582Q B 3 6 5Q HB O3 H7 B 3 8 582Q B 4 8 0,2Q SS QQ 12 SYNC WORD SYNC H B WORD O 0 H1 1/392 MS 0 MS CH1 F 1B F BYTE1 BYTE2 BYTE3 BYTE12 "6-" "6+" 6 MS LEGEND: BNN = PAYLOAD BLOCKS 1-48 HOH = HDSL OVERHEAD SQN = STUFF QUAT 8-BITS BYTE13 BYTE14 BYTE15 BYTE24 CH2 BNN 97/784 MS N8953BDSB Conexant 3-21 3.0 Circuit Descriptions 3.5 HDSL Channel RS8953B/8953SPB HDSL Channel Unit Figure 3-17. 2E1 Frame Format 2E1 FRAME 3503 OR 3505 QUATS 7Q SS QQ 12 1Q 12 X 72.5 = 870Q 5Q BHBB 1O11 2H34 870Q 5Q BHBB 2O22 4H56 870Q 5Q BHBB 3O33 6H78 870Q 0,2Q BSS 4QQ 812 SYNC WORD SYNC H B B WORD O 0 0 H12 1/584 MS 0 MS CH1 ZN 1B CH2 ZN BYTE1 BYTE3 BYTE5 BYTE35 "6-" 6 MS LEGEND: BYTE4 BYTE6 BYTE36 "6+" 8 BITS BYTE2 BNN = PAYLOAD BLOCKS 1-48 HOH = HDSL OVERHEAD SQN = STUFF QUAT BNN 145/1168 MS Figure 3-18. 3E1 Frame Format 3E1 FRAME 2351 OR 2353 QUATS 7Q SS QQ 12 1Q 12 X 48.5 = 582Q 5Q BHBB 1O11 2H34 582Q 5Q BHBB 2O22 4H56 582Q 5Q BHBB 3O33 6H78 582Q 0,2Q BSS 4QQ 812 SYNC WORD SYNC H B B WORD O 0 0 H12 1/392 MS 0 MS CH1 ZN 1B CH2 ZN BYTE1 BYTE4 BYTE7 BYTE34 "6-" 6 MS LEGEND: BYTE5 BYTE8 BYTE35 "6+" 8-BITS BYTE2 BNN = PAYLOAD BLOCKS 1-48 HOH = HDSL OVERHEAD (SW,EOC,CRC...) SQN = STUFF QUAT ZN = Z BITS 1-48 CH3 ZN BYTE3 BYTE6 BYTE9 BYTE36 BNN 97/784 MS 3-22 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.5 HDSL Channel Table 3-3. HDSL Frame Mapping Examples Payload BYTE1 BYTE2 Payload Block (B) BYTE 3-35 2E1 R R 32 BYTES VC-12 V5 R 32 BYTES 3E1-P2MP Channel 0 Channel 0 Channel 0 Channels 1-15 Channel 16 Channel 16 Channel 16 R BYTE36 BYTE37 BYTE 38-71 Payload Block (B+1) Y R R 32 BYTES R Y R C1 C2 0000 RR 32 BYTES Channels 17-31 Channel 0 Channel 0 Channel 0 Channels 1-15 Channel 16 Channel 16 Channel 16 R BYTE 72 BYTE 73-107 Y R R Payload Block (B+2) 32 BYTES R Y R C1 C2 0000 RR 32 BYTES Channels 17-31 Channel 0 Channel 0 Channel 0 Channels 1-15 Channel 16 Channel 16 Channel 16 R BYTE108 BYTE109-143 Payload Block (B+3) Y R R 32 BYTES R Y R C1 C2 0000 S2 IIIIII 31 BYTES Channels 17-31 Channel 0 Channel 0 Channel 0 Channels 1-15 Channel 16 Channel 16 Channel 16 R BYTE 144 Y R Y Channels 17-31 N8953BDSB Conexant 3-23 3.0 Circuit Descriptions 3.5 HDSL Channel RS8953B/8953SPB HDSL Channel Unit 3.5.1 HDSL Transmit Three identical HDSL transmitters accept data and sync from the PCM channel, insert HDSL overhead, and output serially encoded 2B1Q data on TDATn. One HDSL transmitter, shown in Figure 3-19, consists of a transmit payload mapper, HOH multiplexer, STUFF generator and 2B1Q encoder. All transmitter circuits are clocked by BCLKn, where n corresponds to HDSL channels numbered 1, 2, or 3. The HDSL transmit timebase develops 6 ms frame timing based upon the programmed HFRAME_LEN [addr 0xCA] and initial phase alignment established from PCM transmit 6 ms sync plus the TFIFO_WL delay. Each HDSL transmitter automatically manages SYNC, STUFF, and CRC overhead protocols and provides the MPU with write register access for insertion of IND, EOC, and Z-bit overhead bits, but does not automatically manage IND, EOC, or Z-bit protocols. Figure 3-19. HDSL Transmitter Block Diagram Z-bit IND EOC HOH Multiplexer RDATn Sync 2B1Q Align QCLKn TDATn DBANK1 DBANK2 DBANK3 TAUXn Data From TFIFO TLOADn Payload Map Frame Length CRC Scrambler HH_LOOP Stuff Generator CMP TFIFO_RST BCLKn CHn TSYNC (from PCM) / 48 TX 6 ms Stop Start CNT Threshold = Command Register Bit GCLK 3.5.1.1 Transmit Payload Mapper The transmit payload mapper controls the contents of HDSL transmit payload blocks by selecting data for each payload byte from one of five data sources according to selections made in the TMAP Registers [TMAP_1; addr 0x08]. TMAP selects one of five sources for each byte within the payload block: PCM timeslot or F-bit data from the TFIFO, one of three fixed pattern Data Bank Registers (DBANK1-DBANK3), or data sampled from the HDSL auxiliary input (TAUXn). Placement of HDSL Overhead (HOH) bits in the output frame is performed by the HOH multiplexer. HOH bits are grouped into the following categories: SYNC, IND, EOC, CRC, STUFF, and Z-bits. (Refer to Table 3-2 for HOH bit positions within the output frame.) The MPU controls the contents of the HOH bits by writing SYNC_WORD [addr 0xCB], TIND, TEOC, TZBIT (see Table 4-2) and TSTUFF [addr 0xE4] register values. CRC bits are calculated autonomously and inserted into the appropriate HOH bit positions. 3.5.1.2 HOH Multiplexer 3-24 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.5 HDSL Channel 3.5.1.3 CRC Calculation The Cyclic Redundancy Check (CRC) calculation is performed on all transmit data, and the HOH multiplexer inserts the resulting 6-bit CRC into the subsequent output frame. CRC is calculated over all bits in the (N)th frame except the SYNC, STUFF, and CRC bits, and then is inserted into the (N+1)th frame. The MPU can choose to inject CRC errors on a per frame-basis by setting ICRC_ERR [TCMD_1; addr 0x07]. The six CRC bits are calculated as follows: All bits of the (N)th frame, except the 14 SYNC, 6 CRC, and any STUFF bits are used to calculate CRC. A total of 4,682 bits are used, in order of occurrence, to construct a polynomial in X, such that bit 0 of the (N)th frame is the coefficient of the term X4681 and bit 4681 of the (N)th frame is the coefficient of the term X0. 2. The polynomial is multiplied by the factor X6 and the result is divided, modulo 2, by the generator polynomial X6+X+1. Coefficients of the remainder polynomial are used, in order of occurrence, as an ordered set of check bits, CRC1-CRC6, for the (N+1)th frame. Ordering is such that the coefficient of term X5 in the remainder polynomial is check bit CRC1, and the coefficient of term X0 is check bit CRC6. 3. Check bits CRC1-CRC6 contained in a frame are associated with the contents of the preceding frame. When there is no immediately preceding frame, check bits may be assigned any value. 1. 3.5.1.4 Scrambler The scrambler operates at the BCLKn bit rate on all HDSL transmit data, except for the 14-bit SYNC words and the four STUFF bits. The MPU enables the scrambler by setting SCR_EN [TCMD_1; addr 0x06] and selects the scrambler algorithm in SCR_TAP [TCMD_2; addr 0x07]. Two scrambler algorithms are implemented for HTU-R or HTU-C data transmission: * * In the HTU-R to HTU-C direction, the polynomial shall be X-23X-181, where is equal to modulo 2 summation. In the HTU-C to HTU-R direction, the polynomial shall be X-23X-51, where is equal to modulo 2 summation. 3.5.1.5 STUFF Generator Transmit bit stuffing synchronizes the HDSL channel's transmit 6 ms frame period to the PCM channel's 6 ms sync by adding 0 or 4 STUFF bits to the HDSL output frame. The STUFF generator decides whether 0 or 4 STUFF bits are inserted and reports the result of each decision in TX_STUFF [STATUS_3; addr 0x07]. When 4 STUFF bits are inserted, sign/magnitude values are taken from TSTUFF [addr 0xE4]. Stuffing decisions are based on comparison of the phase difference measured between PCM and HDSL 6 ms frame intervals in relation to the programmed STUFF thresholds [STF_THRESH_B; addr 0xD1] and threshold [STF_THRESH_C; addr 0xD3]. If the measured phase difference is equal to or less than threshold B, then no STUFF bits are inserted for that output frame. If the measured phase difference exceeds threshold B and is less than or equal to threshold C, then 4 STUFF bits are inserted. When the measured phase exceeds threshold C, the STUFF generator reports a transmit Stuffing Error, STUFF_ERR [STATUS_3; addr 0x07] and automatically resets the transmit FIFO by performing the TFIFO_RST [addr 0x0D] command. N8953BDSB Conexant 3-25 3.0 Circuit Descriptions 3.5 HDSL Channel RS8953B/8953SPB HDSL Channel Unit The MPU can bypass the STUFF generator and select an alternate source of transmit STUFF bits by setting SLV_STUF [TCMD_2; addr 0x07] and selecting the alternate source in STUFF_SEL [CMD_5; addr 0xE9]. Alternate STUFF bits can be supplied by other HDSL channels, or the MPU can directly manipulate EXT_STUFF [CMD_5; addr 0xE9]. For systems that externally synchronize PCM and HDSL clock phase, the STUFF generator can also be programmed to insert an alternating pattern of 0 and 4 STUFF bits. 3.5.1.6 2B1Q Encoder The 2B1Q (2 Binary, 1 Quaternary) encoder provides the ability to directly interface to the Conexant HDSL transceiver. The 2B1Q encoder converts HDSL data generated internally at the bit rate into sign and magnitude data according to the quaternary alignment provided on the QCLKn input. (Refer to Table 3-4 for sign and magnitude bits used to generate 2B1Q coded outputs on TDATn.) Table 3-4. 2B1Q Encoder Alignment First Bit (Sign) 1 1 0 0 Second Bit (Magnitudes) 0 1 1 0 Quaternary Symbol (Quat) +3 +1 -1 -3 Table 3-5. Z-Bit Definitions Z-bit (Zn) 1 2 3 4 5 6 7 8 to 46 47 48 Loop1 1 0 0 x x x x x x x Loop2 0 1 0 x x x x x x x Loop3 0 0 1 x x x x x x x Comments Pair Identification Pair Identification Pair Identification Not defined Not defined Not defined Not defined Not defined Not defined Not defined 3-26 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.5 HDSL Channel 3.5.1.7 HDSL Auxiliary Transmit The HDSL auxiliary transmit channel provides an alternate source of HDSL payload bytes and optionally, an alternate source for the last 40 Z-bits transmitted in each HDSL frame. Auxiliary transmit data (TAUXn) is sampled by BCLKn whenever TLOADn is active-high, as shown in Figures 3-20 and 3-21. TLOADn is enabled by TAUX_EN [TCMD_2; addr 0x07] and programmed in the Transmit Payload Map Registers [TMAP; addr 0x08]. TLOADn marks specific payload bytes selected in the TMAP registers or marks the last 40 Z-bits depending on the setting of EXT_ZBIT [TCMD_2; addr 0x07]. Figure 3-20. HDSL Auxiliary Channel Payload Timing BCLK QCLK Sign Mag TAUX TLOAD X1 X2 X3 X4 X5 X6 X7 X8 byte1 TAUX Throughput Delay TAUX_EN = 1 EXT_ZBIT = 0 Z1 X1 X2 TDAT SW SW SW SW SW SW SW SW SW SW SW SW SW SW IND IND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 1 NOTE(S): TLOAD shows transmit payload map byte1, TMAP = 11. In this case: TLOAD pulses high during auxiliary input sampling of byte1 in all payload blocks (B1-B48). Figure 3-21. HDSL Auxiliary Channel Z-bit Timing TAUX TLOAD Z 48 Z 9 Z 10 Z 11 TAUX_EN = 1 TAUX Throughput Delay EXT_ZBIT = 1 Z B4 4 Z B5 5 Z B6 6 Z B7 7 Z B8 8 Z Z Z B9 B10 9 10 11 TDAT Z Z Z B47 B48 B1 47 48 1 Z B2 2 Z B3 3 NOTE(S): TAUX throughput delay varies by STUFF bit insertion, shown for illustration only. N8953BDSB Conexant 3-27 3.0 Circuit Descriptions 3.5 HDSL Channel RS8953B/8953SPB HDSL Channel Unit 3.5.2 HDSL Receive The RS8953B contains three identical HDSL receivers, each receiver the same as the one shown in Figure 3-22. The receiver is responsible for frame alignment, destuffing, overhead extraction, descrambling of payload data, error performance monitoring, and payload mapping of HDSL data from received frames into the RFIFO. The receive framer monitors incoming HDSL data to locate SYNC words and to identify frame boundaries for use by other circuits that locate and remove bit stuffing, to check CRC errors, to extract HOH bits and to map payload data to the RFIFO. One of the receivers is configured to act as master reference for the PCM receive channel and from which T1 framing bits are extracted (see MASTER_SEL, CMD_5; addr 0xE9). The master channel also supplies its 6 ms frame reference for DPLL clock recovery. Figure 3-22. HDSL Receiver Block Diagram HDSL Framer CHn RSYNC STUFF Detect CRC CHK HOH Demux HFRAME Count State CNT BCLKn SYNC Detect ROHn RAUXn QCLKn RDATn TDATn 2B1Q Decoder Descrambler Payload Map Data to RFIFO PH_LOOP = Command Register Bit 3.5.2.1 2B1Q Decoder The 2B1Q decoder provides the capability to directly connect to the Conexant HDSL transceiver. The 2B1Q decoder samples and aligns the incoming sign and magnitude data. (Refer to Table 3-6 for 2B1Q mapping.) All three HDSL channels operate independent of one another to allow separate, asynchronous clock signals, to be applied from the system at each HDSL interface. Table 3-6. 2B1Q Decoder Alignment First Bit (Sign) 1 1 0 0 Second Bit (Magnitudes) 0 1 1 0 Quaternary Symbol (Quat) +3 +1 -1 -3 3-28 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.5 HDSL Channel 3.5.2.2 HDSL Receive Framer The HDSL receive framer acquires and maintains synchronization of the HDSL channel and generates pointers that control overhead extraction in the STUFF, CRC and HOH demux circuitry. The MPU initializes the framer to the Out Of Sync state by writing any data value to SYNC_RST [addr 0x63]. From the Out Of Sync state, the framer advances to Sync Acquired when a correct SYNC word is detected. The framer searches all bits received on RDATn to locate a match with one or both of the SYNC word patterns, SYNC_WORD_A [addr 0xCB] or SYNC_WORD_B [addr 0xCC], according to the selection made by FRAMER_EN [RCMD_1; addr 0x60]. For T1 applications, the framer is programmed to search for two different sync word values because separate sync words are transmitted on each HDSL channel to specify the wire pair number. During E1 applications, ETSI requires a common sync word be used for all pairs and Z-bits used to define the wire pair number, although the framer may still be programmed to search for two different sync words in non-standard E1 applications. Due to the possibility of tip/ring connector reversal on each wire pair, all sign bits received on RDATn might be inverted. Therefore, the receive framer searches for both the programmed sync word value and the sign-inverted sync word value. Consequently a maximum of four values of the sync word are used in finding the frame location. If the sync word detected is a sign inverted version of one of the configured sync words, the framer sets the Tip/Ring Inversion (TR_INVERT) status bit [STATUS_1; addr 0x05] and automatically inverts the sign of all quats received on RDATn. N8953BDSB Conexant 3-29 3.0 Circuit Descriptions 3.5 HDSL Channel RS8953B/8953SPB HDSL Channel Unit After detecting a sync word and changing to the Sync Acquired state, the framer progresses through a programmable number of intermediate "Sync Acquired" states before entering the In Sync state. In each "Sync Acquired" state, the framer searches for the previously detected sync word value in one of two locations based upon the absence or presence of the 4 STUFF bits. If the sync word is detected in one of the two possible locations, the STATE_CNT counter is incremented [STATUS_2; addr 0x06]. When STATE_CNT increments to the value selected by the REACH_SYNC criteria [RCMD_1; addr 0x60], the framer changes to the In Sync state. During the Sync Acquired state, if valid sync is not detected at one of the two possible locations, the framer returns to the Out Of Sync state, as shown in Figure 3-23. Figure 3-23. HDSL Receive Framer Synchronization Consecutive SYNC_ACQUIRED States per REACH_SYNC Criteria 1 SYNC No SYNC 2 3 4 5 6 7 8 SYNC SYNC OUT_OF SYNC No SYNC IN_SYNC SYNC No SYNC No SYNC 8 7 6 5 4 3 2 1 Consecutive SYNC_ERRORED States per LOSS_SYNC Criteria 3-30 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.5 HDSL Channel After entering In Sync, the framer either remains In Sync as successive sync words are detected, or regresses to the Sync Errored state if sync pattern errors are found. During Sync Errored states, the number of matching bits from each comparison of received sync word and programmed sync word patterns must meet or exceed the programmed pattern match tolerance specified by THRESH_CORR [RCMD_2; addr 0x61]. If the number of matching bits falls below tolerance, the framer expands the locations searched to quats on either side of the expected location, as shown in Figure 3-24. After detecting a sync pattern error and changing to the Sync Errored state, the framer passes through a programmable number of intermediate Sync Errored states, before entering the Out Of Sync state. STATE_CNT increments for each frame in which sync is not detected until the count reaches the LOSS_SYNC criteria [RCMD_1; addr 0x60] and the framer enters the Out Of Sync state. If at any time during the Sync Errored state the framer detects a completely correct sync word pattern at one of the valid frame locations, then the framer returns to the In Sync state. The ETSI standard recommends the REACH_SYNC = 2 and LOSS_SYNC = 6 framing criteria. Figure 3-24. Threshold Correlation Effect on Expected Sync Locations SYNC Pattern THRESH_CORR SYNC_ERRORED 1 -1q +1q SYNC_ERRORED 2 -1q SYNC_ERRORED 3 +1q -1q +1q T 0 6 ms 12 ms 18 ms SYNC Pattern < THRESH_CORR SYNC_ERRORED 1 -2q +2q SYNC_ERRORED 2 -3q -1q SYNC_ERRORED 3 +1q +3q -4q -2q +2q +4q T 0 6 ms 12 ms 18 ms q = 2 Bits = 1 Quat = Search Location 3.5.2.3 Descrambler The descrambler operates at the BCLKn bit rate on all HDSL receive data, except for the 14-bit SYNC words and 4 STUFF bits. The MPU enables the descrambler by setting the DSCR_EN bit and selects the descrambler algorithm via DSCR_TAP [RCMD_2; addr 0x61]. Two descrambling algorithms are implemented as follows: * * In the HTU-R to HTU-C direction, the polynomial shall be X-23X-181, where is equal to modulo 2 summation. In the HTU-C to HTU-R direction, the polynomial shall be X-23X-51, where is equal to modulo 2 summation. N8953BDSB Conexant 3-31 3.0 Circuit Descriptions 3.5 HDSL Channel RS8953B/8953SPB HDSL Channel Unit 3.5.2.4 CRC Checking The Cyclic Redundancy Check (CRC) error is reported each time the calculated CRC of the (N)th HDSL frame does not match the CRC received in the (N+1)th HDSL frame. Individual block errors are reported in CRC_ERROR [STATUS_2; addr 0x06] and are accumulated in CRC_CNT [addr 0x21]. Each HDSL receiver calculates CRC in the same manner as described for the transmitter. HDSL Overhead (HOH) bits are grouped into the following categories: SYNC, IND, EOC, CRC, and Z-bits. (Refer to Table 3-2 for HOH bit positions within the frame.) HOH demux extracts IND, EOC, and Z-bits from each receive frame and places them into MPU accessible read registers RIND, REOC, and RZBIT (see Table 4-10). The MPU must read the contents of the HOH registers every 6 ms, or as noted. Otherwise, data is overwritten by new received data. The receive payload mapper controls placement of receive payload bytes and Z-bits into the RFIFO as programmed by the RMAP Registers [RMAP; addr 0x64]. The payload mapper aligns itself to incoming HDSL 6 ms frames and selectively transfers payload bytes from the received payload block. The HDSL auxiliary receive channels allow the system to monitor the receive HDSL payload and overhead bits output from the descrambler on RAUXn. The entire received HDSL unscrambled bit stream is output on RAUXn at the BCLKn rate. The MPU selects which category of RAUXn data is marked by ROHn according to programmed values for RAUX_EN and RAZ [CMD_6; addr 0xF3]. ROHn either marks all overhead bits (STUFF, SYNC, HOH, and Z-bits) as shown in Figure 3-25, or marks only the last 40 Z-bits, as shown in Figure 3-26. The system can externally decode ROHn to access specific payload bytes or overhead bits, or to qualify receipt of the last 40 Z-bits. RAUXn and ROHn are disabled (output low) when the respective RAUX_EN is inactive. 3.5.2.5 HOH Demux 3.5.2.6 Receive Payload Mapper 3.5.2.7 HDSL Auxiliary Receive Figure 3-25. HDSL Auxiliary Receive Payload Timing Payload Blocks 1 2 3 4 5 6 7 8 9 10 11 12 ROH BCLK RAUX ROH 4-bit STUFF 14-bit SYNC IND Z1 byte1 RAUX_EN = 1 RAZ = 0 3-32 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Figure 3-26. HDSL Auxiliary Receive Z-bit Timing Payload Blocks 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 13 3.0 Circuit Descriptions 3.5 HDSL Channel ROH BCLK RAUX ROH EOC0-3, CRC1-2, IND2-4, EOC4 Z13 Block 13, byte1 Block 13, byte2 RAUX_EN = 1 RAZ = 1 N8953BDSB Conexant 3-33 3.0 Circuit Descriptions 3.6 PRA Function RS8953B/8953SPB HDSL Channel Unit 3.6 PRA Function This document specifies requirements for using the integrated service digital network. Figure 3-27 shows an overview of the HDSL link between the Termination Equipment (TE) and the Exchange Termination (ET). Figure 3-27. An Overview of the PRA Transfer of Data RS8953B RSER G RMSYNC TE TSER TMSYNC M G M G E-bits E-bits HDSL E-bits E-bits RESER RMSYNC M G M TMSYNC ET RS8953B TSER NOTE(S): TE - Termination Equipment ET - Exchange Termination M - Monitor ET - Exchange Termination 3.6.1 Transferring Data from HDSL to RSER The following functions are available when transferring data from HDSL to RSER: CRC4 monitoring, E-bit insertion, E-bits counter, and CRC4 generator. When CRC4 monitoring is enabled, E1 data--which is received via HDSL--is checked for error blocks by using the CRC4 procedure, as specified in CCITT recommendation G.704[9], subclause 2.3.3. The check result, represented in E-bits, is inserted into the data stream in the appropriate location. When CRC4 monitoring is disabled, two options are available for E-bit insertion: New values are inserted for the E-bits, or the E1 data stream remains untouched. If new values are inserted, an external CPU must be used to program the value of these bits. The E-bit insertion mode is repeated each E1 frame until another value is programmed, or until another mode is selected. The E-bits counter is continuously enabled and causes an 8-bit counter to count the amount of E-bits reflected by the E1 stream. This information is received via HDSL. This counter wraps around on full count. The value of the counter needs to be accessible to an external CPU. The counter is reset upon reading the value. 3-34 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 3.0 Circuit Descriptions 3.6 PRA Function Enabling the CRC4 generator causes CRC4 regeneration of the E1 data (RSER). The result is inserted into the data stream in the appropriate location in accordance with the CRC4 procedure specified in CCITT recommendation G.704. If the CRC4 generator is disabled, the following options are available: New values are inserted for the CRC4 bits, or you can leave the CRC4 bits untouched. If new values are inserted, an external CPU must be used to program the value of these bits. To implement this, a simple storage register can be used to insert four bits into the data stream. The CRC4 insertion is repeated each E1 frame until another value is programmed, or until another mode is selected. 3.6.2 Definitions of Detection Algorithms When transferring data from HDSL or RSER, the following definitions of detection algorithms apply: * Normal operational frames: The algorithm will be in accordance with CCITT Recommendation G.706[7]. This condition is indicated by one bit in a register. Loss of frame alignment: The algorithm will be in accordance with CCITT Recommendation G.706[7]. This condition is indicated by one bit in a register. Code words: Code words consist of four SA6 bits and the A-bit. A new code is declared only when the value of the SA6 bits and the A-bit remains the same in the last eight frames. The code word is then stored in a 5-bit register. * * 3.6.3 Inserting Data Transferred from HDSL to RSER When transferring data from HDSL to RSER, bits are transferred in the following manner: * Each A-bit and SA4, SA5, SA7, and SA8 bit may be selected as transparent or non-transparent. For non-transparent bits, the new value of the certain bit is stored in a register and is inserted into the correct location of the data stream (RSER). The SA6 bits may be transferred either transparently or non-transparently. Selecting transparent or non-transparent affects all four SA6 bits. For non-transparent transfers, the new value of the bits is stored in a register and is inserted into the correct location of the data stream (RSER). The FAS bits may be transferred either transparently or non-transparently. Selecting transparent or non-transparent affects all the FAS bits. For non-transparent bits, the FAS value is inserted into the correct location of the data stream (RSER). * * 3.6.4 Transferring Data from TSER to HDSL When CRC4 monitoring is enabled, data received from TSER is checked for error blocks by using the CRC4 procedure, as specified in CCITT recommendation G.704[9], subclause 2.3.3. The check result, reflected by the E-bits, is inserted into the correct location of the data stream. N8953BDSB Conexant 3-35 3.0 Circuit Descriptions 3.6 PRA Function RS8953B/8953SPB HDSL Channel Unit If CRC4 monitoring is disabled, new values must be inserted into the E-bits, or the E-bits must pass transparently (from the input TSER). If new values are inserted, these bits are obtained by enabling an external CPU to program a 2-bit register. The E-bits counter is continuously enabled and causes an 8-bit counter to count the amount of E-bits errors. It wraps around on full count. An external CPU must be available to read the value of the counter. The counter is reset upon reading the value. The CRC4 generator, when enabled, causes the E1 data (TSER) to be fed into a CRC4 generator. The CRC bits are inserted into the correct location of the data stream (TSER) according to the CRC4 procedure which is specified in CCITT recommendation G.704. If the CRC4 generator is disabled, new values can be inserted for the CRC4 bits, or the CRC4 bits can be passed transparently (from the input TSER). If new values are inserted, the new value is stored in a 4-bits register and is repeatedly inserted into the correct location of the data stream. This insertion process is continuously repeated until a new mode is selected. 3.6.5 Inserting Data Transferred from TSER to HDSL * Each A-bit and SA4, SA5, SA7, and SA8 bit may be selected as transparent or non-transparent. For non-transparent bits, the new value of the certain bit is stored in a register and is inserted into the correct location of the data stream (TSER). The SA6 bits may be transferred either transparently or non-transparently. Selecting transparent or non-transparent affects all four SA6 bits. For non-transparent transfers, the new value of the bits is stored in a register and is inserted into the correct location of the data stream (TSER). The FAS bits may be transferred either transparently or non-transparently. Selecting transparent or non-transparent affects all the FAS bits. For non-transparent bits, the FAS value is inserted into the correct location of the data stream (TSER). The FAS is a constant pattern. * * 3-36 Conexant N8953BDSB 4 4.0 Registers All RS8953B registers are read-only or write-only. For registers that contain less than 8 bits, assigned bits reside in LSB positions; unassigned bits are ignored during write cycles and are indeterminate during read cycles. The LSB in all registers is bit position 0. All registers are randomly accessible except for the 64 transmit routing table entries, the 64 receive combination table entries, and the 16 receive signaling table entries which are written sequentially to a single register address. After power-up, register initialization is required only for populated HDSL channels. Command and status registers related to disconnected HDSL channels can be ignored (all HDSL inputs are internally pulled high). The single-pair version (RS8953SPBEPF and RS8953SPBEPJ) only supports HDSL Channel 1. HDSL Channels 2 and 3 are not usable. Although only one HDSL channel is usable, the internal registers are not changed from the three HDSL channel versions. This means that the registers should be programmed with the same value as if only HDSL Channel 1 was used in a three-channel version. This allows the three-channel version to be used for development, and without a software change, a single-pair version used for production. N8953BDSB Conexant 4-1 4.0 Registers RS8953B/8953SPB HDSL Channel Unit Register Types The Microprocessor Unit (MPU) must read and write real-time registers, and receive and transmit EOC, IND, Z-bit, and status registers within a prescribed time interval (1-6 ms) after their respective HDSL channel's 6 ms frame interrupt. This must be done to avoid reading or writing transitory data values. Failure to read real-time registers within the prescribed interval results in a loss of data. The MPU writes to non-real time command registers which are event-driven and which are written when the system initializes, changes modes, or responds to an error condition. Whenever data is written to a RS8953B register, the data is first written to the Shadow Write Register [SHADOW_WR; addr 0x3B], and then the data is transferred from the SHADOW_WR register to the addressed register. For diagnostics, software can read-verify the last write cycle by reading the SHADOW_WR register. This will confirm that the data was written to the SHADOW_WR register, but does not confirm that the data was transferred to the addressed register. If the Write Pulse Width specification is not met, then the data may not be correctly transferred from the SHADOW_WR register to the addressed register. To prevent transitory write data in non-real time command registers, the MPU can first write the desired data value to the SHADOW_WR register, and then write the same data to the desired register. MPU reads may be interrupt event driven, polled, or a combination of both, thereby allowing the choice to be dictated by system architecture. Polled procedures can avoid reading transitory real-time data by monitoring the Interrupt Request Register [IRR; address 0x1F] bits to determine when a particular group of registers has been updated. Interrupt driven and polled procedures must complete reading within the prescribed 1-6 ms interval following HDSL frame interrupts. RS8953B command, status, and real-time registers are divided into three groups: Common, Transmit, and Receive registers. Common registers effect overall operation, primarily the PCM channel and the DPLL. Three identical groups of Transmit and Receive registers only affect operation or report status of the respective HDSL channel. Transmit registers reference data flow from the PCM channel to the HDSL channel outputs, while Receive registers reference data flow from the HDSL channel to the PCM channel outputs. RS8953B initialization and error handling routines, written in C-language, are available via the terms of the HDSL software license agreement. The addresses shown for each Transmit and Receive register or bit description reference only HDSL Channel 1. (See the Summary tables at the start of each section to find address locations for HDSL channels 2 and 3.) Register Groups 4-2 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.1 Address Map 4.1 Address Map The channel column (CHn) of Table 4-1 indicates which HDSL channel number (n = 1,2,3) is associated with each register. Common registers are indicated by a `C' in the CHn column. Table 4-1. Register Summary Address Map (1 of 6) Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B CHn 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- Write Register TEOC_LO TEOC_HI TIND_LO TIND_HI TZBIT_1 TFIFO_WL TCMD_1 TCMD_2 TMAP_1 TMAP_2 TMAP_3 TMAP_4 TMAP_5 TFIFO_RST SCR_RST TMAP_6 TMAP_7 TMAP_8 TMAP_9 -- -- -- -- -- -- -- -- -- Page Ref. 4-10 4-10 4-10 4-10 4-10 4-12 4-12 4-13 4-15 4-15 4-15 4-15 4-15 4-17 4-17 4-16 4-16 4-16 4-16 -- -- -- -- -- -- -- -- -- CHn 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 C C C C Read Register REOC_LO REOC_HI RIND_LO RIND_HI RZBIT_1 STATUS_1 STATUS_2 STATUS_3 REOC_LO REOC_HI RIND_LO RIND_HI RZBIT_1 STATUS_1 STATUS_2 STATUS_3 REOC_LO REOC_HI RIND_LO RIND_HI RZBIT_1 STATUS_1 STATUS_2 STATUS_3 RZBIT_2 RZBIT_3 RZBIT_4 RZBIT_5 Page Ref. 4-53 4-54 4-54 4-54 4-54 4-55 4-57 4-58 4-53 4-54 4-54 4-54 4-54 4-55 4-57 4-58 4-53 4-54 4-54 4-54 4-54 4-55 4-57 4-58 4-55 4-55 4-55 4-55 N8953BDSB Conexant 4-3 4.0 Registers 4.1 Address Map RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map (2 of 6) Addr 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33-0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D-0x3F 0x40 0x41 0x42 0x43 CHn -- -- -- -- 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- -- -- -- -- -- -- 3 3 3 3 Write Register -- -- -- -- TEOC_LO TEOC_HI TIND_LO TIND_HI TZBIT_1 TFIFO_WL TCMD_1 TCMD_2 TMAP_1 TMAP_2 TMAP_3 TMAP_4 TMAP_5 TFIFO_RST SCR_RST TMAP_6 TMAP_7 TMAP_8 TMAP_9 -- -- -- -- -- -- -- TEOC_LO TEOC_HI TIND_LO TIND_HI Page Ref. -- -- -- -- 4-10 4-10 4-10 4-10 4-10 4-12 4-12 4-13 4-15 4-15 4-15 4-15 4-15 4-17 4-17 4-16 4-16 4-16 4-16 -- -- -- -- -- -- -- 4-10 4-10 4-10 4-10 CHn C C C C C 1 1 -- -- -- -- -- C 2 2 -- -- -- -- -- C 3 3 -- C C C C C -- C C C C Read Register RZBIT_6 BER_METER BER_STATUS IRR RESID_OUT_HI CRC_CNT FEBE_CNT -- -- -- -- -- RESID_OUT_LO CRC_CNT FEBE_CNT -- -- -- -- -- IMR CRC_CNT FEBE_CNT -- PHS_ERR MSYNC_PHS_LO MSYNC_PHS_HI SHADOW_WR ERR_STATUS -- TX_PRA_CTRL0 TX_PRA_CTRL_1 TX_PRA_MON1 TX_PRA_E_CNT Page Ref. 4-55 4-60 4-61 4-61 4-62 4-58 4-59 -- -- -- -- -- 4-62 4-59 4-59 -- -- -- -- -- 4-62 4-59 4-59 -- 4-63 4-63 4-63 4-64 4-64 -- 4-65 4-66 4-67 4-67 4-4 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map (3 of 6) Addr 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x70 0x71 0x72 0x73 0x74 0x80 0x81 4.0 Registers 4.1 Address Map CHn 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C 2 2 Write Register TZBIT_1 TFIFO_WL TCMD_1 TCMD_2 TMAP_1 TMAP_2 TMAP_3 TMAP_4 TMAP_5 TFIFO_RST SCR_RST TMAP_6 TMAP_7 TMAP_8 TMAP_9 RCMD_1 RCMD_2 RFIFO_RST SYNC_RST RMAP_1 RMAP_2 RMAP_3 ERR_RST RSIG_LOC RMAP_4 RMAP_5 RMAP_6 TX_PRA_CTRL0 TX_PRA_CTRL1 TX_BITS_BUFF1 TX_PRA_TMSYNC_OFFSET TX_BITS_BUFF0 RCMD_1 RCMD_2 Page Ref. 4-10 4-12 4-12 4-13 4-15 4-15 4-15 4-15 4-15 4-17 4-17 4-16 4-16 4-16 4-16 4-19 4-20 4-21 4-21 4-22 4-22 4-22 4-23 4-23 4-22 4-22 4-23 4-69 4-70 4-71 4-71 4-72 4-19 4-20 CHn -- C C C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C C Read Register -- TX_PRA_CODE TX_PRA_MON0 TX_PRA_MON2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RX_PRA_CTRL0 RX_PRA_CTRL1 Page Ref. 4-67 4-68 4-68 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4-73 4-74 N8953BDSB Conexant 4-5 4.0 Registers 4.1 Address Map RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map (4 of 6) Addr 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xB0 0xB1 0xB2 0xB4 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 CHn 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 C C C C C C C C C C C C Write Register RFIFO_RST SYNC_RST RMAP_1 RMAP_2 RMAP_3 ERR_RST RSIG_LOC RMAP_4 RMAP_5 RMAP_6 RCMD_1 RCMD_2 RFIFO_RST SYNC_RST RMAP_1 RMAP_2 RMAP_3 ERR_RST RSIG_LOC RMAP_4 RMAP_5 RMAP_6 RX_PRA_CTRL0 RX_PRA_CTRL1 RX_BITS_BUFF1 RX_BITS_BUFF0 TFRAME_LOC_LO TFRAME_LOC_HI TMF_LOC RFRAME_LOC_LO RFRAME_LOC_HI RMF_LOC MF_LEN MF_CNT Page Ref. 4-21 4-21 4-22 4-22 4-22 4-23 4-23 4-22 4-22 4-23 4-19 4-20 4-21 4-21 4-22 4-22 4-22 4-23 4-23 4-22 4-22 4-23 4-77 4-78 4-79 4-79 4-26 4-26 4-26 4-26 4-27 4-27 4-27 4-28 CHn C C C C C C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Read Register RX_BITS_BUFF1 RX_PRA_E_CNT RX_PRA_CRC_CNT RX_PRA_CODE RX_PRA_MON0 RX_PRA_MON2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Page Ref. 4-75 4-75 4-75 4-76 4-76 4-76 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4-6 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map (5 of 6) Addr 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 4.0 Registers 4.1 Address Map CHn C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C Write Register FRAME_LEN_LO FRAME_LEN_HI HFRAME_LEN_LO SYNC_WORD_A SYNC_WORD_B RFIFO_WL_LO RFIFO_WL_HI STF_THRESH_A_LO STF_THRESH_A_HI STF_THRESH_B_LO STF_THRESH_B_HI STF_THRESH_C_LO STF_THRESH_C_HI DPLL_RESID_LO DPLL_RESID_HI DPLL_FACTOR DPLL_GAIN DPLL_PINI DBANK_1 DBANK_2 DBANK_3 TZBIT_2 TZBIT_3 TZBIT_4 TZBIT_5 TZBIT_6 TSTUFF CMD_1 CMD_2 CMD_3 CMD_4 CMD_5 FILL_PATT IMR Page Ref. 4-28 4-28 4-29 4-31 4-31 4-31 4-32 4-33 4-33 4-33 4-33 4-33 4-34 4-35 4-36 4-36 4-37 4-38 4-39 4-39 4-40 4-11 4-11 4-11 4-11 4-11 4-40 4-44 4-45 4-46 4-47 4-47 4-40 4-51 CHn -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Read Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Page Ref. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- N8953BDSB Conexant 4-7 4.0 Registers 4.1 Address Map RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map (6 of 6) Addr 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7-0xFF F8 F9 FA FB CHn C C C C C C C C C C C -- 2 2 3 3 Write Register ICR ROUTE_TBL COMBINE_TBL BER_RST PRBS_RST RX_RST RSIG_TBL CMD_6 CMD_7 HFRAME_LEN_HI DPLL_RST -- HFRAME_2LEN_LO HFRAME2_LEN_HI HFRAME3_LEN_LO HFRAME3_LEN_HI Page Ref. 4-51 4-41 4-42 4-52 4-52 4-52 4-43 4-48 4-49 4-30 4-38 -- 4-30 4-30 4-30 4-31 CHn -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Read Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Page Ref. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4-8 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.2 HDSL Transmit 4.2 HDSL Transmit HDSL Channel 1 (CH1) Base Address 0x00 HDSL Channel 2 (CH2) 0x20 HDSL Channel 3 (CH3) 0x40 Table 4-2. HDSL Transmit Write Registers CH1 0x00 0x01 0x02 0x03 0x04 CH2 0x20 0x21 0x22 0x23 0x24 0xDF 0xE0 0xE1 0xE2 0xE3 CH3 0x40 0x41 0x42 0x43 0x44 Register Label TEOC_LO TEOC_HI TIND_LO TIND_HI TZBIT_1 TZBIT_2 TZBIT_3 TZBIT_4 TZBIT_5 TZBIT_6 Bits 8 5 8 5 8 8 8 8 8 8 8 7 6 8 8 8 8 8 8 8 8 8 -- -- Description Transmit EOC Bits Transmit EOC Bits Transmit IND Bits Transmit IND Bits Transmit Z-bits Common Transmit Z-bits Common Transmit Z-bits Common Transmit Z-bits Common Transmit Z-bits Common Transmit Z-bits Transmit FIFO Water Level Configuration Configuration Payload Map Payload Map Payload Map Payload Map Payload Map Payload Map Payload Map Payload Map Payload Map Transmit FIFO Reset Scrambler Reset 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0F 0x10 0x11 0x12 0x0D 0x0E 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2F 0x30 0x31 0x32 0x2D 0x2E 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4F 0x50 0x51 0x52 0x4D 0x4E TFIFO_WL TCMD_1 TCMD_2 TMAP_1 TMAP_2 TMAP_3 TMAP_4 TMAP_5 TMAP_6 TMAP_7 TMAP_8 TMAP_9 TFIFO_RST SCR_RST N8953BDSB Conexant 4-9 4.0 Registers 4.2 HDSL Transmit RS8953B/8953SPB HDSL Channel Unit 0x00--Transmit Embedded Operations Channel (TEOC_LO) 7 6 5 4 TEOC[7:0] 3 2 1 0 0x01--Transmit Embedded Operations Channel (TEOC_HI) 7 -- 6 -- 5 -- 4 3 2 TEOC[12:8] 1 0 TEOC[12:0] The Transmit Embedded Operations Channel (TEOC) holds 13 EOC bits for transmission in the next frame. (Refer to Table 3-2 for EOC bit positions within the frame.) The HOH multiplexer samples TEOC coincident with the respective HDSL channel's transmit 6 ms frame interrupt. Unmodified registers repeatedly output their contents in each frame. 0x02--Transmit Indicator Bits (TIND_LO) 7 6 5 4 TIND[7:0] 3 2 1 0 0x03--Transmit Indicator Bits (TIND_HI) 7 -- 6 -- 5 -- 4 3 2 TIND[12:8] 1 0 TIND[12:0] The Transmit Indicator holds 13 IND bits for transmission in the next frame and includes the FEBE bit (TIND[1]). (Refer to Table 3-2 for IND bit positions within the frame.) The HOH multiplexer samples TIND coincident with the respective HDSL channel's transmit 6 ms frame interrupt. Unmodified registers repeatedly output their contents in each frame. TIND[0] is transmitted first. NOTE: The RS8953B does not automatically output FEBE. Proper transmit of FEBE requires the MPU to copy the CRC_ERR bit from STATUS_2 [addr 0x06] to TIND[1]. 0x04--Transmit Z-Bits (TZBIT_1) 7 6 5 4 TZBIT[7:0] 3 2 1 0 4-10 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.2 HDSL Transmit 0xDF--Transmit Z-Bits (TZBIT_2) 7 6 5 4 TZBIT[15:8] 3 2 1 0 0xE0--Transmit Z-Bits (TZBIT_3) 7 6 5 4 TZBIT[23:16] 3 2 1 0 0xE1--Transmit Z-Bits (TZBIT_4) 7 6 5 4 TZBIT[31:24] 3 2 1 0 0xE2--Transmit Z-Bits (TZBIT_5) 7 6 5 4 TZBIT[39:32] 3 2 1 0 0xE3--Transmit Z-Bits (TZBIT_6) 7 6 5 4 TZBIT[47:40] 3 2 1 0 TZBIT[47:0] Transmit Z-bits is applicable only in E1_MODE [CMD_1; addr 0xE5]; otherwise, Z-bit registers are ignored. TZBIT[47:0] holds 48 Z-bits for transmission in the first bit of each of the 48 payload blocks. (See Figure 3-16 for Z-bit positions within the frame.) The first eight Z-bits are individually output for each channel from TZBIT_1. The last 40 Z-bits are output to all channels from a single set of TZBIT_2-TZBIT_6. NOTE: The system may also supply the last 40 Z-bits individually for each HDSL transmit channel from the TAUXn inputs by setting TAUX_EN and EXT_ZBIT [TCMD_2; addr 0x07]. N8953BDSB Conexant 4-11 4.0 Registers 4.2 HDSL Transmit RS8953B/8953SPB HDSL Channel Unit TZBIT_1 is sampled on the respective transmit 6 ms frame interrupt, giving the MPU up to 6 ms to modify the TZBIT_1 contents for output in next frame. TZBIT_2 through TZBIT_6 are sampled during their respective output times, giving the MPU up to 1 ms after the transmit frame interrupt to update TZBIT_2; 2 ms to update TZBIT_3; and 5 ms to update TZBIT_6. This assumes all HDSL transmit frames are output aligned. If differential delay exists between the transmit channels (as controlled by TFIFO_WL; addr 0x05), then less time is available to update TZBIT_2-TZBIT_6. Unmodified registers repeatedly output their contents in each frame. TZBIT[0] is transmitted first. 0x05--Transmit FIFO Water Level (TFIFO_WL) 7 6 5 4 TFIFO_WL[7:0] 3 2 1 0 TFIFO_WL[7:0] Transmit FIFO Water Level contains the number of TCLK cycles to delay from the PCM 6 ms frame to the start of the HDSL transmit SYNC word. A value of zero equals 1 TCLK delay. Minimum water level values compensate for time to unload one timeslot (8 HDSL bits), time to load one timeslot (8 PCM bits), the amount of differential delay created by the PCM router (up to 96 PCM bits in T1 mode), and a phase jitter tolerance (8 to 16 PCM bits). (Refer to TFIFO_WL description in the PCM Channel Section.) 0x06--Transmit Command Register 1 (TCMD_1) Real-time commands (Bits 0-5) are sampled by the HOH multiplexer on the respective transmit frame to affect operation in the next outgoing frame. HOH_EN, TWO_LEVEL, and FORCE_ONE command bit combinations provide the transmit data encoding options needed to perform standard HDSL channel startup procedures. 7 -- 6 TX_ERR_EN 5 FORCE_ONE 4 HOH_EN 3 SYNC_SEL 2 ICRC_ERR 1 TWO_LEVEL 0 SCR_EN SCR_EN Scrambler Enable--All transmit HDSL channel bits, except SYNC and STUFF bits, are scrambled per the SCR_TAP setting in TCMD_2[0x47]. Otherwise, transmit data passes through the scrambler unchanged. 0 = Scrambler bypassed 1 = Scrambler enabled TWO_LEVEL Two Level Transmit Enable--All 2B1Q encoder magnitude bit outputs are forced to 0 to comply with standard requirements for a two-level transmit signal. 0 = Four-level 2B1Q encoder operation 1 = Two-level 2B1Q encoder operation ICRC_ERR Inject CRC Error--Logically inverts the six calculated CRC bits in the next frame. 0 = Normal CRC transmission 1 = Transmit errored CRC SYNC_SEL SYNC Word Select--Selects one of two SYNC words, SYNC_WORD_A or SYNC_WORD_B [addresses 0xCB-0xCC], for transmission in the next frame. 0 = SYNC_WORD_A is transmitted 1 = SYNC_WORD_B is transmitted 4-12 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit HOH_EN 4.0 Registers 4.2 HDSL Transmit HDSL Overhead Enable--The HOH multiplexer inserts EOC, IND, and CRC bits. Otherwise, transmit overhead bits, except SYNC and STUFF, are forced to all 1s. HOH_EN = 0 select transmission of two-level or four-level scrambled 1s. 0 = HOH transmitted as all 1s 1 = Normal HOH transmission FORCE_ONE Force All 1s Payload--Transmit payload data bytes are replaced by all 1s. FORCE_ONE and HOH_EN are both set to enable output of a four-level framed, scrambled-1s signal. 0 = Normal payload transmission 1 = Force all 1s payload TX_ERR_EN Transmit Error Interrupt Enable--Transmit errors request TX_ERR interrupt and report TXn_ERR status upon detection of TFIFO or TSTUFF errors [STATUS_3; addr 0x07]. Disabled channels are prevented from activating INTR*, or setting TX_ERR [IRR; addr 0x1F]. Transmit errors are always latched in ERR_STATUS [addr 0x3C] regardless of TX_ERR_EN. 0 = Disable transmit error interrupts 1 = Enable transmit error interrupts 0x07--Transmit Command Register 2 (TCMD_2) 7 -- 6 STUF_CNTR_ MODE 5 EXT_ZBIT 4 REPEAT_EN 3 TAUX_EN 2 SLV_STUF 1 SCR_TAP 0 HH_LOOP HH_LOOP Loopback to HDSL on the HDSL Side--Receive HDSL data (RDATn) is switched to transmit HDSL data (TDATn) to accomplish a loopback of the HDSL channel on the HDSL side. Loopback data is switched at I/O pins and does not alter HDSL receive operations. 0 = Normal transmit 1 = TDATn supplied by RDATn pin SCR_TAP Scrambler Tap--Selects which delay stage, 5th or 18th, to tap for feedback in the transmit scrambler. The system's HDSL terminal type dictates which scrambler tap should be selected. 0 = HTU-C or LTU terminal type, scrambler taps 5th delay stage 1 = HTU-R or NTU terminal type, scrambler taps 18th delay stage SLV_STUF Slave STUFF Bits--Transmit STUFF bits are either generated by a local stuffing mechanism or are slaved to an alternate source of STUFF bits. If enabled, the slave STUFF source is chosen by STUFF_SEL in Common CMD_5 [addr 0xE9]. 0 = Local STUFF bit generation 1 = Slave STUFF bits to STUFF_SEL source TAUX_EN Transmit Auxiliary Enable--Transmit auxiliary data from the TAUX1-TAUX3 inputs are sampled when the respective TLOAD1-TLOAD3 outputs are active. TAUX samples and TLOAD activation are selected for each payload byte via the transmit payload map [TMAP; addr 0x08]. When TAUX_EN is low, TAUX inputs are ignored and TLOAD outputs are forced low. 0 = Disable TAUX and TLOAD signals 1 = Enable TAUX and TLOAD signals N8953BDSB Conexant 4-13 4.0 Registers 4.2 HDSL Transmit REPEAT_EN RS8953B/8953SPB HDSL Channel Unit Enable Repeater Mode--When set in both CH1 and CH2, REPEAT_EN cross-connects HDSL payload, SYNC, STUFF, and Z-bits from receive to transmit to implement a single pair repeater. REPEAT_EN has no effect in CH3. Transmit 6 ms frames are forced to align to cross-connected receive 6 ms frames. HOH bits (EOC, IND, and CRC) are inserted by each channel's transmit HOH multiplexer to allow for translation of repeater specific IND bits. HDSL bit clocks, BCLK1, and BCLK2 can operate with separate phase, but must be identical in long-term frequency. Receive payload from CH1 and CH2 can still be mapped and PCM combined, but transmit PCM inputs are ignored. 0 = Normal transmit 1 = Cross-connect CH1 and CH2 EXT_ZBIT Enable External Z-bits--Is set in conjunction with TAUX_EN when the system supplies the last 40 Z-bits for transmission from TAUXn input. 0 = Last 40 Z-bits supplied by TZBIT2-TZBIT6 registers 1 = Last 40 Z-bits supplied by TAUXn STUF_CNTR_MODE Selects the operation of the counter that measures the phase difference between the PCM and HDSL line clocks. If this bit is cleared in any of the registers for the three channels, the stuffing generator is in a mode ion which the counter is not allowed to wrap around. In this mode, the stuffing algorithm is based on only current conditions. When this bit is set in each of the registers for the 3 channels, the stuffing generator is in a mode in which the counter is allowed to wrap around. In this mode, the stuffing algorithm is based on both previous decisions and current conditions. This changes the stuffing pattern, which causes reduced low frequency wander and increased high frequency jitter. 0 = Increased wander and decreased jitter (in any register) 1 = Decreased wander and increased jitter (in all three registers) 4-14 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.3 Transmit Payload Mapper 4.3 Transmit Payload Mapper The Transmit Payload Map (TMAP_1-TMAP_9) determines whether HDSL payload bytes (byte1 through byte36) are supplied from PCM timeslots, DBANK registers, or the HDSL auxiliary channel data. All routed timeslots to a given channel's TFIFO must also be mapped out of the TFIFO. The RS8953B sequentially maps payload and cannot rearrange byte ordering but allows payload from the DBANK registers to be interleaved with PCM data. If PCM transmit data is input-aligned to MSYNC, then the first TMAP byte to select PCM receives the first routed PCM timeslot from the transmit PCM multiframe (i.e., PCM frame 0 maps to HDSL payload block 1). If PCM data is not aligned to MSYNC, then payload bytes mapped from the TFIFO are not aligned to PCM timeslots and HDSL payload blocks are not aligned to PCM frames. In T1 mode, TMAP must be programmed to supply F-bits, by enabling one extra byte of payload at the end of the payload block. 0x08--Transmit Payload Map (TMAP_1) 7 6 5 4 3 2 1 0 BYTE4 TMAP[1:0] BYTE3 TMAP[1:0] BYTE2 TMAP[1:0] BYTE1 TMAP[1:0] 0x09--Transmit Payload Map (TMAP_2) 7 6 5 4 3 2 1 0 BYTE8 TMAP[1:0] BYTE7 TMAP[1:0] BYTE6 TMAP[1:0] BYTE5 TMAP[1:0] 0x0A--Transmit Payload Map (TMAP_3) 7 6 5 4 3 2 1 0 BYTE12 TMAP[1:0] BYTE11 TMAP[1:0] BYTE10 TMAP[1:0] BYTE9 TMAP[1:0] 0x0B--Transmit Payload Map (TMAP_4) 7 6 5 4 3 2 1 0 BYTE16 TMAP[1:0] BYTE15 TMAP[1:0] BYTE14 TMAP[1:0] BYTE13 TMAP[1:0] 0x0C--Transmit Payload Map (TMAP_5) 7 6 5 4 3 2 1 0 BYTE20 TMAP[1:0] BYTE19 TMAP[1:0] BYTE18 TMAP[1:0] BYTE17 TMAP[1:0] N8953BDSB Conexant 4-15 4.0 Registers 4.3 Transmit Payload Mapper RS8953B/8953SPB HDSL Channel Unit 0x0F--Transmit Payload Map (TMAP_6) 7 6 5 4 3 2 1 0 BYTE24 TMAP[1:0] BYTE23 TMAP[1:0] BYTE22 TMAP[1:0] BYTE21 TMAP[1:0] 0x10--Transmit Payload Map (TMAP_7) 7 6 5 4 3 2 1 0 BYTE28 TMAP[1:0] BYTE27 TMAP[1:0] BYTE26 TMAP[1:0] BYTE25 TMAP[1:0] 0x11--Transmit Payload Map (TMAP_8) 7 6 5 4 3 2 1 0 BYTE32 TMAP[1:0] BYTE31 TMAP[1:0] BYTE30 TMAP[1:0] BYTE29 TMAP[1:0] 0x12--Transmit Payload Map (TMAP_9) 7 6 5 4 3 2 1 0 BYTE36 TMAP[1:0] BYTE35 TMAP[1:0] BYTE34 TMAP[1:0] BYTE33 TMAP[1:0] Transmit Payload Map code selects one of four data sources for HDSL payload bytes. A maximum of 18 map codes, corresponding to payload byte1 through byte36, are programmed for each HDSL channel. If the payload block length is less than 36 bytes, TMAP codes of the upper bytes are unused. TMAP[1:0] 00 01 10 11 Transmit HDSL Payload Source PCM data from TFIFO DBANK_1 DBANK_2 DBANK_3(1, 2) Notes: 1. When DBANK_3 and TAUX_EN [TCMD_2; addr 0x07] are selected, TLOADn output is active and TAUXn supplies data during selected payload byte. 2. When DBANK_3, TAUX_EN and EXT_ZBIT [TCMD_2; addr 0x07] are selected, TLOADn output is active and TAUXn supplies data during the last 40 Z-bits. 4-16 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.3 Transmit Payload Mapper The following configurations can cause the HDSL frame to become corrupted: DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte #33. TFIFO or CBank_1 is the source of data for HDSL payload byte #0. The LSB of the DBank_1 pattern is equal to one (1). or DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte #33. DBank_2 is the source of data for HDSL payload byte #0. The LSB of the DBank_2 pattern is equal to one (1). or DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte #33. DBank_3 is the source of data for HDSL payload byte #0. The LSB of the DBank_3 pattern is equal to one (1). 0x0D--Transmit FIFO Reset (TFIFO_RST) Writing any data value to TFIFO_RST empties the TFIFO, forces the HDSL transmitter to resample the Transmit FIFO Water Level [TFIFO_WL; addr 0x05], and realigns the HDSL channel's transmit 6 ms frame to the PCM 6 ms frame. The MPU must write TFIFO_RST after modifying the TFIFO_WL value, the Transmit Payload Map [TMAP; addr 0x08], or the PCM Routing Table [ROUTE_TBL; addr 0xED] each time PCM MultiFrame Sync (TMSYNC) experiences a change of frame alignment and whenever the TFIFO reports an overflow, underflow, or slip error. The RS8953B asserts TFIFO_RST automatically whenever a transmit STUFF error is detected. NOTE: Each write to TFIFO_RST may cause TFIFO errors in the next three subsequent HDSL frames. Therefore, the MPU must ignore up to three TFIFO errors reported in the respective channel for the next 3 HDSL frames after writing the TFIFO_RST command. 0x0E--Scrambler Reset (SCR_RST) Writing any data value to SCR_RST sets the 23 stages of the scrambler LFSR to 0x000001. SCR_RST is used during the Conexant production test to verify scrambler operation, and is not required during normal operation. N8953BDSB Conexant 4-17 4.0 Registers 4.4 HDSL Receive RS8953B/8953SPB HDSL Channel Unit 4.4 HDSL Receive HDSL Channel 1 (CH1) Base Address 0x60 HDSL Channel 2 (CH2) 0x80 HDSL Channel 3 (CH3) 0xA0 Table 4-3. HDSL Receive Write Registers CH1 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x70 0x71 CH2 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x70 0x71 CH3 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xA0 0xA1 Register Label RCMD_1 RCMD_2 RFIFO_RST SYNC_RST RMAP_1 RMAP_2 RMAP_3 RMAP_4 RMAP_5 RMAP_6 ERR_RST RSIG_LOC Bits 8 8 - - 6 6 6 6 6 6 - 4 Name/Description Configuration Configuration Receive FIFO Reset Receive Framer Reset Payload Map Payload Map Payload Map Payload Map Payload Map Payload Map Error Count Reset Receive Signaling Location Three identical groups of write-only registers configure the HDSL receivers, and control the mapping of HDSL payload bytes into the receiver elastic stores (RFIFO). Configuration registers define each HDSL receive framer's criteria for loss and recovery of frame alignment by selecting the number of detected SYNC word errors used to declare loss of sync or needed to acquire sync. Refer to the Framer Synchronization State Diagram, Figure 3-23. Frame alignment criteria are programmable to meet different standard application requirements. 4-18 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.4 HDSL Receive 0x60--Receive Command Register 1 (RCMD_1) 7 6 5 4 LOSS_SYNC[2:0] 3 2 1 REACH_SYNC[2:0] 0 FRAMER_EN[1:0] REACH_SYNC[2:0] Reach Sync Framing Criteria--Contains the number of consecutive HDSL frames in which the SYNC word is detected before the receive framer moves from the OUT_OF_SYNC to the IN_SYNC state. REACH_SYNC determines the number of SYNC_ACQUIRED intermediate states the framer must pass through during recovery of frame sync. ETSI standard criteria requires two consecutive frames containing SYNC. REACH_SYNC 000 001 010 011 100 101 110 111 IN_SYNC Criteria 1 frame containing SYNC 2 consecutive frames 3 consecutive frames 4 consecutive frames 5 consecutive frames 6 consecutive frames 7 consecutive frames 8 consecutive frames LOSS_SYNC[2:0] Loss of Sync Framing Criteria--Contains the number of consecutive HDSL frames in which the SYNC word is not detected before the receive framer moves from the IN_SYNC to the OUT_OF_SYNC state. LOSS_SYNC determines the number of SYNC_ERRORED intermediate states the framer must pass through during loss of frame sync. ETSI standard criteria requires six consecutive frames without SYNC word detected. LOSS_SYNC 000 001 010 011 100 101 110 111 OUT_OF_SYNC Criteria 1 frame not containing SYNC 2 consecutive frames 3 consecutive frames 4 consecutive frames 5 consecutive frames 6 consecutive frames 7 consecutive frames 8 consecutive frames FRAMER_EN[1:0] Receive Framer Enable--Instructs the receive framer to search for one or both of the SYNC word patterns programmed in SYNC_WORD_A [addr 0xCB] or SYNC_WORD_B [addr 0xCC]. If enabled to search for both, then the SYNC acquisition state proceeds with only the first detected pattern. When disabled, the framer does not count errors or generate interrupts. FRAMER_EN 00 01 10 11 Receive Framer Search Disabled; framer forced to OUT_OF_SYNC SYNC_WORD_A SYNC_WORD_B Both SYNC_WORD_A and SYNC_WORD_B N8953BDSB Conexant 4-19 4.0 Registers 4.4 HDSL Receive RS8953B/8953SPB HDSL Channel Unit 0x61--Receive Command Register 2 (RCMD_2) 7 RX_ERR_EN 6 PH_LOOP 5 DSCR_EN 4 DSCR_TAP 3 2 1 0 THRESH_CORR[3:0} THRESH_CORR[3:0] SYNC Threshold Correlation--Upon the receive framer's entry to a Sync Errored state, the number of SYNC word locations searched is determined by the result of the previous states' threshold correlation. During an In Sync state, the framer searches the two most probable SYNC word locations at 6 ms 1 quat, corresponding to 0 or 4 STUFF bits. One of the two locations searched must correctly match the entire 14-bit SYNC word or the framer enters a Sync Errored state. The highest number of matching bits found among the search locations is compared to the selected THRESH_CORR value to determine whether the framer should expand the number of search locations. If the highest number of matching bits meets or exceeds the threshold, but was not a complete match, the framer progresses to the next Sync Errored state and continues to each of the two most probable locations. Otherwise, the framer progresses to the next Sync Errored state, increments the number of locations to be searched, and examines quats on either side of the prior search locations. For example, if the location with the highest number of matching bits is below the threshold during In Sync, then the framer enters the first Sync Errored state and searches from the prior location at 6 ms 2 quats, and at exactly 6 ms. The effect of threshold correlation on the number of search locations is depicted in Figure 3-24. THRESH_CORR 1010 1011 1100 1101 1110 SYNC Threshold Correlation 10 or more out of 14 bits 11 or more out of 14 bits 12 or more out of 14 bits 13 or more out of 14 bits 14 out of 14 bits DSCR_TAP Descrambler Tap--Selects which delay stage, 5th or 18th, to tap for feedback in the descrambler. The system's terminal type dictates which tap should be selected. 0 = HTU-C or LTU terminal type, descrambler selects tap 18 1 = HTU-R or NTU terminal type, descrambler selects tap 5 Descrambler Enable--When enabled, all receive HDSL channel data, except SYNC and STUFF bits, are descrambled per the DSCR_TAP setting. Otherwise the data passes through the descrambler unchanged. DSCR_EN also determines whether RSER and RAUXn data are descrambled. 0 = Descrambler bypassed 1 = Descrambler enabled DSCR_EN PH_LOOP Loopback to PCM on HDSL Side--Transmit HDSL data (TDATn) is connected back towards the PCM interface to accomplish a loopback of the PCM channel on the HDSL side. Receive HDSL data (RDATn) is ignored, but HDSL transmit continues without interruption. PH_LOOP requires the descrambler and scrambler to use the same tap, as opposed to their normal opposing tap selection. 0 = Normal receive 1 = RDATn supplied by TDATn 4-20 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit RX_ERR_EN 4.0 Registers 4.4 HDSL Receive Receive Error Interrupt Enable--Receive errors request RX_ERR interrupt and report RXn_ERR status upon detection of RFIFO errors [STATUS_1; addr 0x05], framer state transitions or error counter overflows [STATUS_2; addr 0x06]. Disabled channels are prevented from activating INTR*, or setting RX_ERR [IRR; addr 0x1F]. Receive errors are always latched in ERR_STATUS [addr 0x3C] regardless of RX_ERR_EN. 0 = Disable RX_ERR interrupts 1 = Enable RX_ERR interrupts 0x62--Receive Elastic Store FIFO Reset (RFIFO_RST) Writing any data value to RFIFO_RST empties the RFIFO and forces the payload mapper to realign HDSL bytes with respect to the receive HDSL 6 ms frame. The MPU must write RFIFO_RST after modifying the Receive Payload Map [RMAP; addr 0x64] or the Combination Table [COMBINE_TBL; addr 0xEE] each time the receive framer changes from the SYNC_ACQUIRED to the IN_SYNC state [STATUS_2; addr 0x06]; whenever a RFIFO error is reported [STATUS_1; addr 0x05]; and after the DPLL has settled. Writing RFIFO_RST corrupts up to three receive PCM frames worth of data. 0x63--Receive Framer Synchronization Reset (SYNC_RST) Writing any data value to SYNC_RST forces the receive framer to the OUT_OF_SYNC state, which restarts the SYNC word search and causes the framer to issue an RX_ERR interrupt. The MPU must write SYNC_RST after modifying FRAMER_EN [RCMD_2; addr 0x61], SYNC_WORD_A, or SYNC_WORD_B. Writing SYNC_RST to the master HDSL channel corrupts up to three receive PCM frames worth of data and may cause a DPLL error interrupt. N8953BDSB Conexant 4-21 4.0 Registers 4.5 Receive Payload Mapper RS8953B/8953SPB HDSL Channel Unit 4.5 Receive Payload Mapper The Receive Payload Map (RMAP_1-RMAP_6) controls placement of HDSL payload bytes (byte1-byte36) into the RFIFO by instructing the mapper to place or discard payload bytes from the received payload block. Payload bytes are mapped sequentially from each payload block and cannot be rearranged. Payload is subsequently combined [COMBINE_TBL; addr 0xEE] at the RFIFO outputs to reconstruct the PCM channel. RMAP is programmed to discard bytes within the payload block that are not needed for PCM reconstruction. In T1 mode, RMAP must be programmed to choose which HDSL channel supplies F-bits, by enabling one extra byte of payload at the end of the payload block. 0x64--Receive Payload Map (RMAP_1) 7 -- 6 -- 5 4 3 RMAP[5:0] 2 1 0 0x65--Receive Payload Map (RMAP_2) 7 -- 6 -- 5 4 3 RMAP[11:6] 2 1 0 0x66--Receive Payload Map (RMAP_3) 7 -- 6 -- 5 4 3 RMAP[17:12] 2 1 0 0x69--Receive Payload Map (RMAP_4) 7 -- 6 -- 5 4 3 RMAP[23:18] 2 1 0 0x6A--Receive Payload Map (RMAP_5) 7 -- 6 -- 5 4 3 RMAP[29:24] 2 1 0 4-22 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.5 Receive Payload Mapper 0x6B--Receive Payload Map (RMAP_6) 7 -- 6 -- 5 4 3 RMAP[35:30] 2 1 0 RMAP[35:0] Receive Payload Map--Six registers hold a 36-bit value to define which of the received HDSL payload bytes (byte1 through byte36) are placed into the RFIFO. RMAP[0] corresponds to the first HDSL payload byte (byte1). In T1 mode, F-bits are mapped by enabling one extra byte after the last payload mapped byte. For example, RMAP[12] controls F-bit mapping to the RFIFO in 2T1 applications. If RMAP[x] = 0, discard payload byte(x+1) If RMAP[x] = 1, map payload byte(x+1) to RFIFO 0x67--Error Count Reset (ERR_RST) Writing any data value to ERR_RST clears the receive CRC Error Counter [CRC_CNT; addr 0x21], the receive Far End Block Error Counter [FEBE_CNT; addr 0x22], and consequently clears the Counter Overflow (CRC_OVR) and FEBE_OVR bits [STATUS_2; addr 0x06]. ERR_RST clears the error counters immediately and must be issued within 6 ms after the respective receive frame interrupt in order to avoid clearing unreported errors. No other receive errors (CRC_ERR, RFIFO, or RX_STUFF) are affected by ERR_RST. 0x68--Receive Signaling Location (RSIG_LOC) 7 -- 6 -- 5 -- 4 -- 3 2 RSIG_LOC[3:0] 1 0 RSIG_LOC[3:0] Receive Signaling Location--Is applicable only if RSIG_EN [CMD_6; addr 0xF3] enables LTU grooming in a 2E1 or 3E1 Point-to-Multipoint (P2MP) system. The Receive Signaling Table [RSIG_TBL; addr 0xF2] compensates for differential frame delays between two or three remote sites by delaying the current PCM receive frame sync according to the RSIG_LOC frame delay values for each HDSL channel. RSIG_TBL uses each RSIG_LOC frame delay to locate frame 0 and to transfer ABCD signaling from the respective channel. RSIG_LOC sets the number of frame delays, from 1 to 16 frames, therefore RSIG_TBL needs to delay the current receive PCM frame in order to locate frame 0 of the respective channel. A value of zero signifies a one frame delay. A one frame delay corresponds to frame 0 occurring in the first HDSL payload block. RSIG_LOC values are calculated for each channel from the remote sites measurement of RMSYNC Phase [MSYNC_PHS; addr 0x39]: t ( RMP ) RSIG_LOC = truncate ---------------------------------- - 1 FRAME_LEN where: FRAME_LEN RSIG_LOC truncate [] t(RMP) = PCM bits per frame = Frame delay = Integer part only = Remote sites RMSYNC to MSYNC phase (measured in PCM bits) N8953BDSB Conexant 4-23 4.0 Registers 4.5 Receive Payload Mapper NOTE: RS8953B/8953SPB HDSL Channel Unit If RSIG_LOC is negative, then the programmed value equals 15. EOC messaging capability may be used by the NTU to transfer the results of the RMSYNC phase measurement back to the LTU. Remote sites must align HDSL transmit frames to their respective PCM Transmit Multiframe Sync (TMSYNC) for this equation to remain valid. 4-24 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.6 PCM Formatter 4.6 PCM Formatter Table 4-4. PCM Formatter Write Registers Address 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 Register Label TFRAME_LOC_LO TFRAME_LOC_HI TMF_LOC RFRAME_LOC_LO RFRAME_LOC_LO RMF_LOC MF_LEN MF_CNT FRAME_LEN_LO FRAME_LEN_LO Bits 8 1 6 8 1 6 6 6 8 1 TSER Frame Bit Location TSER Frame Bit Location Name/Description TSER Multiframe Location RSER Frame Bit Location RSER Frame Bit Location RSER Multiframe Location PCM Multiframe Length PCM Multiframes per HDSL Frame PCM Frame Length PCM Frame Length The PCM formatter supports connections to many types of PCM channels by allowing the system to define the PCM bus format and sync timing characteristics. PCM frame length, multiframe length, and PCM multiframes per HDSL frame are programmed in the PCM formatter registers to define receive and transmit timebases. Programmed frame and multiframe lengths for both timebases allows the RS8953B to continue operating at appropriate intervals when PCM transmit sync or HDSL receive sync references are lost, and when RS8953B acts as the PCM bus master. The transmit timebase controls the routing of PCM timeslots into the transmit FIFOs, while the receive timebase controls the extraction of PCM timeslots out of the receive FIFOs. The number of multiframes per HDSL frame is needed to generate PCM 6 ms timebases used for transmit bit stuffing and Digital Phase Lock Loop (DPLL) receive clock recovery. PCM formatter configuration registers also define the PCM timing relationships between transmit data (TSER, INSDAT) and sync (TMSYNC, MSYNC), and receive data (RSER) and sync (RMSYNC). TMSYNC is delayed by a programmed number of bits and frames to create the MSYNC output signal. MSYNC is then used to locate the first bit (bit 0) of a frame, and the first frame (frame0) of a multiframe at the TSER input. MSYNC is always used to align both PCM and HDSL transmit timebases, regardless of whether TMSYNC is applied. RMSYNC is output from the receive PCM timebase after it is delayed by a programmed number of bits and frames. NOTE: The internal PCM receive timebase is frame and multiframe aligned with respect to the master HDSL channel's receive 6 ms frames [refer to RFIFO_WL; addr 0xCD]. The internal PCM receive timebase is not affected by programmed bit and frame delays for RMSYNC. N8953BDSB Conexant 4-25 4.0 Registers 4.6 PCM Formatter RS8953B/8953SPB HDSL Channel Unit 0xC0--TSER Frame Bit Location (TFRAME_LOC_LO) TFRAME_LOC and TMF_LOC work in conjunction to define the location of bit 0, frame 0, at the TSER data input with respect to TMSYNC. 7 6 5 4 3 2 1 0 TFRAME_LOC[7:0] 0xC1--TSER Frame Bit Location (TFRAME_LOC_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 TFRAME_LOC[8] TFRAME_LOC[8:0] TSER Frame Bit Location--Establishes the number of PCM bit delays, in the range of 1 to 512 bits, from the rising edge of TMSYNC until PCM bit 0 is sampled on TSER. A value of 0 delays TMSYNC by three TCLK periods. If TMSYNC and TSER are input aligned, where TMSYNC's rising edge coincides with TSER input of PCM bit 0, then TFRAME_LOC is programmed to equal the PCM frame length minus three. The following examples assume TMSYNC and TSER are input aligned: PCM Frame Length E1 = 256 bits T1 = 193 bits 64x64 = 512 bits TFRAME_LOC[8:0] = Decimal (hex) 253 (0x0FD) 190 (0x0BE) 509 (0x1FD) 0xC2--TSER Multiframe Bit Location (TMF_LOC) 7 -- 6 -- 5 4 3 TMF_LOC[5] 2 1 0 TMF_LOC[5:0] TSER Multiframe Bit Location--TMF_LOC sets the number of frame delays, in the range of 1 to 64 frames, from TMSYNC (delayed by TFRAME_LOC) until PCM frame 0 is present on TSER. A value of 0 delays TMSYNC by one PCM frame. If TMSYNC and TSER are input aligned, TMF_LOC is programmed to equal the multiframe length minus two. The following examples assume TMSYNC's rising edge coincides with PCM frame 0 input on TSER: PCM Multiframe Length E1 = 16 frames SF = 12 frames ESF = 24 frames TMF_LOC[5:0] = Decimal (hex) 14 (0x0E) 10 (0x0A) 22 (0x16) 0xC3--RSER Frame Bit Location (RFRAME_LOC_LO) RFRAME_LOC and RMF_LOC work in conjunction to define which RSER bit and frame location is marked by the RMSYNC output. Typically, RMSYNC is used as a PCM multiframe sync signal and is programmed to mark during RSER output of bit0, frame0. However, any RSER bit location within the received multiframe can be marked as desired. 4-26 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.6 PCM Formatter 7 6 5 4 3 2 1 0 RFRAME_LOC[7:0] 0xC4--RSER Frame Bit Location (RFRAME_LOC_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 RFRAME_LOC[8] RFRAME_LOC[8:0] RSER Frame Bit Location--Establishes the number of PCM bit delays, in the range of 1 bit to 512 bits, from the internal PCM receive timebase's output of bit 0 to the rising edge of RMSYNC. Due to internal bit delays, a value of two will delay RMSYNC by one RCLK period, in which case the rising edge of RMSYNC coincides with output of RSER bit 1. If the system desires RMSYNC to mark RSER bit0, then RFRAME_LOC is programmed to equal 1. The following examples assume RMSYNC is desired to mark RSER bit 0: PCM Frame Length E1 = 256 bits T1 = 193 bits 64x64 = 512 bits RFRAME_LOC[8:0] = Decimal (hex) 1 (0x01) 1 (0x01) 1 (0x01) 0xC5--RSER Multiframe Bit Location (RMF_LOC) 7 -- 6 -- 5 4 3 RMF_LOC[5:0] 2 1 0 RMF_LOC[5:0] RSER Multiframe Bit Location--Establishes the number of PCM frame delays, in the range of 1 to 64 frames, from the internal PCM receive timebase's output of frame 0 to the rising edge of RMSYNC. Due to internal frame delay, a value of one delays RMSYNC by one PCM frame. RMF_LOC enacts the RMSYNC frame delay after the RFRAME_LOC bit delay. If the system desires RMSYNC to mark RSER frame 0, then RMF_LOC is programmed to equal 0. The following examples assume RMSYNC is desired to mark RSER frame 0: PCM Multiframe Length E1 = 16 frames SF = 12 frames ESF = 24 frames RMF_LOC[5:0] = Decimal (hex) 0 (0x00) 0 (0x00) 0 (0x00) 0xC6--PCM Multiframe Length (MF_LEN) 7 -- 6 -- 5 4 3 MF_LEN[5:0] 2 1 0 N8953BDSB Conexant 4-27 4.0 Registers 4.6 PCM Formatter MF_LEN[5:0] RS8953B/8953SPB HDSL Channel Unit PCM Multiframe Length--Contains the number of PCM frames in one PCM multiframe, in the range of 1 to 64 frames. A value of zero selects one frame per multiframe, which causes TMSYNC and RMSYNC to operate at the PCM frame rate. 0xC7--PCM Multiframes per HDSL Frame (MF_CNT) 7 -- 6 -- 5 4 3 MF_CNT[5:0] 2 1 0 MF_CNT[5:0] PCM Multiframes per HDSL Frame--Contains the number of PCM multiframes in one HDSL 6 ms frame, in the range of 1 to 64 multiframes. A value of zero selects one multiframe per HDSL frame. MF_CNT operates in conjunction with FRAME_LEN and MF_LEN to create transmit and receive PCM 6 ms timebases which are needed to perform transmit bit stuffing and DPLL receive clock recovery. The RS8953B requires the product of MF_LEN and MF_CNT to always equal 48 to match the number of HDSL payload blocks in an HDSL frame. For example: PCM Multiframe E1 =16 frames SF = 12 frames ESF = 24 frames Unframed = 1 frame MF_LEN[5:0] 15 (0x0F) 11 (0x0B) 23 (0x17) 0 (0x00) MF_CNT[5:0] 2 (0x02) 3 (0x03) 1 (0x01) 47 (0x2F) Product 16 x 3 = 48 12 x 4 = 48 24 x 2 = 48 1 x 48 = 48 0xC8--PCM Frame Length (FRAME_LEN_LO) 7 6 5 4 3 2 1 0 FRAME_LEN[7:0] 0xC9--PCM Frame Length (FRAME_LEN_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 FRAME_LEN[8] FRAME_LEN[8:0] PCM Frame Length--Contains the number of bits in one PCM frame, in the range of 16 to 512 bits. A value of 255 selects 256 bit PCM frame length. The selected value includes payload (number of timeslots x 8) and framing bits. For example, FRAME_LEN value equals 192 (0xC0) to select a 193-bit T1 frame. 4-28 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.7 HDSL Channel Configuration 4.7 HDSL Channel Configuration Table 4-5. HDSL Channel Configuration Write Registers Address 0xCA 0xF5 0xF8 0xF9 0xFA 0XFB 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 Register Label HFRAME_LEN_LO HFRAME_LEN_HI HFRAME2_LEN_LO HFRAME2_LEN_HI HFRAME3_LEN_LO HFRAME3_LEN_HI SYNC_WORD_A SYNC_WORD_B RFIFO_WL_LO RFIFO_WL_HI STF_THRESH_A_LO STF_THRESH_A_HI STF_THRESH_B_LO STF_THRESH_B_HI STF_THRESH_C_LO STF_THRESH_C_HI Bits 8 1 8 1 8 1 7 7 8 2 8 2 8 2 8 2 Name/Description HDSL Frame Length HDSL Frame Length HDSL Frame Length HDSL Frame Length HDSL Frame Length HDSL Frame Length SYNC Word A (sign only) SYNC Word B (sign only) RX FIFO Water Level RX FIFO Water Level Stuffing Threshold A Stuffing Threshold A Stuffing Threshold B Stuffing Threshold B Stuffing Threshold C Stuffing Threshold C 0xCA--HDSL Frame Length (HFRAME_LEN_LO) 7 6 5 4 3 2 1 0 HFRAME_LEN[7:0] N8953BDSB Conexant 4-29 4.0 Registers 4.7 HDSL Channel Configuration RS8953B/8953SPB HDSL Channel Unit 0xF5--HDSL Frame Length (HFRAME_LEN_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 HFRAME_LEN[8] HFRAME_LEN[8:0] HDSL Payload Block Length--Contains the number of BCLKn bits, in the range of 16 to 512, that are transmitted and received in an HDSL payload block. Each payload block is comprised of an integer number of 8-bit bytes plus an additional F-bit or Z-bit. The RS8953B repeats the payload block length 48 times to form one HDSL frame. A value of 15 selects a 16-bit payload block length; therefore, the programmed value of HFRAME_LEN equals eight times the number of payload bytes. For example, a value of 96 (0x60) selects a 12-byte T1 payload or 144 (0x90) selects an 18-byte E1 payload. Value written to HFRAME_LEN are copied into HFRAME2_LEN and HFRAME3_LEN. In theory, the HDSL frame length can be different for each loop. But if the HDSL frame lengths are not close to the same value, RFIFO errors will probably occur. For this reason, we do not recommend different values for the HDSL frame length. 0xF8--HDSL Frame Length (HFRAME2_LEN_LO) 7 6 5 4 3 2 1 0 HFRAME_LEN[7:0] 0xF9--HDSL Frame Length (HFRAME2_LEN_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 HFRAME_LEN[8] HFRAME2_LEN[8:0] HDSL Payload Block Length--Contains the number of BCLK2 bits in the range of 16 to 512, that are transmitted and received in an HDSL payload block for Channel 2. In theory, the HDSL frame length can be different for each loop. But if the HDSL frame lengths are not close to the same value, RFIFO errors will probably occur. For this reason, we do not recommend different values for the HDSL frame length. 0xFA--HDSL Frame Length (HFRAME3_LEN_LO) 7 6 5 4 3 2 1 0 HFRAME_LEN[7:0] 4-30 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.7 HDSL Channel Configuration 0xFB--HDSL Frame Length (HFRAME3_LEN_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 HFRAME_LEN[8] HFRAME3_LEN[8:0] HDSL Payload Block Length--Contains the number of BCLK3 bits, in the range of 16 to 512, that are transmitted and received in an HDSL payload block for Channel 3. In theory, the HDSL frame length can be different for each loop. But if the HDSL frame lengths are not close to the same value, RFIFO errors will probably occur. For this reason, we do not recommend different values for the HDSL frame length. 0xCB--SYNC Word A (SYNC_WORD_A) 7 -- 6 5 4 3 SYNC_WORD_A[6:0] 2 1 0 SYNC_WORD_A[6:0] SYNC Word A--Holds the 7 sign bits (+/-) of the 7-quat (14-bit) transmit and receive SYNC word. Transmit SYNC word magnitude bits are forced to 0. SYNC_WORD_A[0] is the sign bit of the first transmit quat. Sign precedes magnitude on the transmit data (TDATn) output. The receive framer searches HDSL data (RDATn) for patterns matching SYNC_WORD_A and/or SYNC_WORD_B according to the criteria selected in FRAMER_EN [RCMD_1; addr 0x60]. 0 = Negative sign bit 1 = Positive sign bit 0xCC--SYNC Word B (SYNC_WORD_B) 7 -- 6 5 4 3 SYNC_WORD_B[6:0] 2 1 0 SYNC_WORD_B[6:0] SYNC Word B--Holds the 7 sign bits (+/-) of the transmit and receive SYNC word. It performs the same function as SYNC_WORD_A (see above). SYNC_WORD_B is provided for 2T1 applications that use different SYNC patterns on each HDSL channel for loop identification purposes. Transmit selection of SYNC word A or B is programmed by SYNC_SEL [TCMD_1; addr 0x06]. 0 = Negative sign bit 1 = Positive sign bit 0xCD--RX FIFO Water Level (RFIFO_WL_LO) 7 6 5 4 RFIFO_WL[7:0] 3 2 1 0 N8953BDSB Conexant 4-31 4.0 Registers 4.8 Transmit Bit Stuffing Thresholds RS8953B/8953SPB HDSL Channel Unit 0xCE--RX FIFO Water Level (RFIFO_WL_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 RFIFO_WL[9:8] 0 RFIFO_WL[8:0] Receive FIFO Water Level--Sets the RCLK bit delay from the master HDSL channel's receive 6 ms frame to the PCM receive 6 ms frame. The delay is programmed in RCLK bit intervals, in the range of 1 to 1,024 bits. A value of zero equals one RCLK bit delay. The minimum RFIFO_WL value must allow sufficient time to elapse for payload to pass through the RFIFO. The maximum RFIFO_WL must not allow more than 185 bits to be present in the RFIFO at any given time. 4.8 Transmit Bit Stuffing Thresholds The STUFF generator in each HDSL transmit channel makes bit stuffing decisions based upon phase comparisons of the difference between PCM transmit 6 ms frames and HDSL transmit 6 ms frames, with respect to two programmable Stuffing Thresholds [STF_THRESH and STF_THRESH_C; addr 0xD1-D4]. Results of the phase comparisons determine whether the HDSL channel's STUFF generator inserts 0 STUFF bits or 4 STUFF bits in the outgoing HDSL frame. Inserted STUFF bit values are supplied by TSTUFF [addr 0xE4]. The General Purpose Clock (GCLK) is used to quantize phase differences between PCM and HDSL frame starting locations. GCLK is developed from the MCLK frequency (fMCLK), PLL Multiplication (PLL_MUL) and PLL Division (PLL_DIV) scale factors [CMD_1; addr 0xE5]. The STUFF generator makes bit stuffing decisions using the following criteria: PCM to HDSL Phase Difference < STF_THRESH_A STF_THRESH_A < STF_THRESH_C STF_THRESH_C (1) Inserted STUFF Bits 0 4 4 (1)4 A phase difference measured to be equal to or in excess of STF_THRESH_C is reported as a transmit stuffing error in STUFF_ERR [STATUS_3; addr 0x07]. Stuffing threshold values are programmed to set the nominal and maximum tolerable phase difference in units of GCLK phase. STUFF insertion accounts for 4 HDSL bits worth of phase error and STUFF thresholds are set to equal 16 or 24 HDSL bits worth of phase at the BCLKn frequency (fHDSL), as shown in the following equation: n x f MCLK PLL_MUL StuffingThreshold = ------------------------ x -------------------------f HDSL PLL_DIV 4-32 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.8 Transmit Bit Stuffing Thresholds where: n = 8 for STF_THRESH_A n = 12 for STF_THRESH_B n = 24 for STF_THRESH_C 0xCF--Bit Stuffing Threshold A (STF_THRESH_A_LO) 7 6 5 4 3 2 1 0 STF_THRESH_A[7:0] 0xD0--Bit Stuffing Threshold A (STF_THRESH_A_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 0 STF_THRESH_A[9:8] STF_THRESH_A[8:0] Bit Stuffing Threshold A--Contains the number of GCLK cycles equaling 8 HDSL bit times. If the phase measured from PCM to HDSL 6 ms frames is a positive value greater than or equal to STF_THRESH_A, then 4 STUFF bits are inserted in the outgoing HDSL frame. If the phase is a positive value less then STF_THRESH_A, then STUFF bits are not inserted in the outgoing HDSL frame. If the phase is a negative value, then the phase tolerance on HDSL, PCM, or GCLK inputs is exceeded and the STUFF generator reports STUFF_ERR [STATUS_3; addr 0x07]. 0xD1--Bit Stuffing Threshold B (STF_THRESH_B_LO) 7 6 5 4 3 2 1 0 STF_THRESH_B[7:0] 0xD2--Bit Stuffing Threshold B (STF_THRESH_B_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 0 STF_THRESH_B[9:8] STF_THRESH_B[8:0] Bit Stuffing Threshold B--Contains the number of GCLK cycles equaling 12 HDSL bit times. 0xD3--Bit Stuffing Threshold C (STF_THRESH_C_LO) 7 6 5 4 3 2 1 0 STF_THRESH_C[7:0] N8953BDSB Conexant 4-33 4.0 Registers 4.8 Transmit Bit Stuffing Thresholds RS8953B/8953SPB HDSL Channel Unit 0xD4--Bit Stuffing Threshold C (STF_THRESH_C_HI) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 0 STF_THRESH_C[9:8] STF_THRESH_C[8:0] Bit Stuffing Threshold C--Contains the number of GCLK cycles equal to 24 HDSL bit times. If the phase measured from PCM to HDSL 6 ms frames is a positive value less than STF_THRESH_C, then 4 STUFF bits are inserted in the outgoing frame. If the phase is a positive value greater than or equal to STF_THRESH_C, then the phase tolerance on HDSL, PCM, or GCLK inputs is exceeded and the STUFF generator reports STUFF_ERR [STATUS_3; addr 0x07]. NOTE: STF_THRESH_C must be greater than STF_THRESH_B by a value of 4 HDSL bit times (4 x HDSL / GCLK) but not greater than a value of 0x3FF. 4-34 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.9 DPLL Configuration 4.9 DPLL Configuration Table 4-6. DPLL Configuration Write Registers Address 0xD5 0xD6 0xD7 0xD8 0xDB 0xF6 Register Label DPLL_RESID_LO DPLL_RESID_HI DPLL_FACTOR DPLL_GAIN DPLL_PINI DPLL_RST Bits 8 8 8 7 8 -- DPLL Residual DPLL Residual DPLL Factor DPLL Gain Name/Description DPLL Phase Detector Init (optional for RS8953B) DPLL Phase Detector Reset The DPLL synthesizes the PCM Receive Clock (RCLK) output from the 60 through 80 MHz Reference Clock (HFCLK) generated internally by PLL multiplication of MCLK, or input directly on MCLK [see PLL_MUL and PLL_DIS in CMD_1; addr 0xE5]. HFCLK must operate in the 60 to 80 MHz frequency range, but requires no specific phase or frequency relationship to the PCM or HDSL channels. The nominal frequency (fPCM) of RCLK is synthesized by setting the DPLL_FACTOR and DPLL_RESID values according to the integer and fractional results of the following formula: f MCLK x PLL_MUL [INTEGER.FRACTION] = ------------------------------------------------ 2 x f PCM where: fMCLK fPCM INTEGER FRACTION PLL_MUL PLL_DIV = MCLK input frequency = RCLK output frequency desired = Integer part of result [DPLL_FACTOR; addr 0xD7] = Fractional part of result [DPLL_RESID; addr 0xD5] = PLL multiplication factor [CMD_1; addr 0xE5] = PLL scale factor [CMD_1; addr 0xE5] The DPLL phase detector operates from the 10-15 MHz General Purpose Clock (GCLK) which equals HFCLK divided by PLL scale factor: f MCLK x PLL_MUL GCLK = ------------------------------------------------ PLL_DIV 0xD5--DPLL Residual (DPLL_RESID_LO) 7 6 5 4 3 2 1 0 DPLL_RESID[7:0] N8953BDSB Conexant 4-35 4.0 Registers 4.9 DPLL Configuration RS8953B/8953SPB HDSL Channel Unit 0xD6--DPLL Residual (DPLL_RESID_HI) 7 6 5 4 3 2 1 0 DPLL_RESID[15:8] DPLL_RESID[15:0] DPLL Residual--Works in conjunction with DPLL_FACTOR to define the DPLL nominal free-running frequency in Open Loop Mode or the DPLL initial frequency in Closed Loop Mode [DPLL_NCO in CMD_5; addr 0xE9]. The DPLL_RESID value is sampled by the DPLL only after the MPU writes RX_RST [address 0xF1], or after the master HDSL channel's receive framer transitions to an IN_SYNC state. DPLL_RESID = round ( FRACTION x 65535 ) DPLL_FACTOR = 257 - INTEGER where: round ( ) = Round to nearest integer FRACTION = Fraction from INTEGER.FRACTION calculation INTEGER = Integer from INTEGER.FRACTION calculation Assuming MCLK operates at eight times the BCLKn frequency (16 times symbol rate) and RCLK is desired to operate at standard T1 or E1 clock rates. The following examples show HTU application values for DPLL_RESID and DPLL_FACTOR: HTU 2T1 3E1 2E1 PLL_MUL 11 11 8 PLL_DIV 6 6 6 DPLL_FACTOR 0xEB 0xF1 0xEF DPLL_RESID 0x578B 0xD7FF 0x4000 0xD7--DPLL Factor (DPLL_FACTOR) 7 6 5 4 3 2 1 0 DPLL_FACTOR[7:0] DPLL_FACTOR[7:0] DPLL Factor--Works in conjunction with DPLL_RESID. 4-36 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.9 DPLL Configuration 0xD8--DPLL Gain (DPLL_GAIN) 7 -- 6 5 DC_GAIN[2:0] 4 3 2 DC_INTEG[3:0] 1 0 DPLL_GAIN[7:0] DPLL Gain--Filtering is controlled by two DC parameters: DC_GAIN, which represents proportional loop gain, and DC_INTEG, which represents the filter's integration coefficient. The DPLL closed loop bandwidth is programmed to be in the range of 0.2 Hz to 3 Hz. The following approximations are used to calculate DC parameters for a desired DPLL bandwidth: BW DC_GAIN = ------------------- x 2 17 N x 26.5 ( BW ) 2 2 15 DC_INTEG = --------------- x ------N 26.5 2 where: N = RCLK output frequency / 64000 BW = DPLL closed loop bandwidth (in Hz) Specific DC parameter values are programmed according to the following tables: DC_GAIN[2:0] 000 001 010 011 100 101 110 111 DC_INTEG[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010-1110 1111 RS8953B 25 26 27 28 29 210 211 212 RS8953B 2-4 2-3 2-2 2-1 1 21 22 23 24 25 26 0 (Type I) N8953BDSB Conexant 4-37 4.0 Registers 4.9 DPLL Configuration RS8953B/8953SPB HDSL Channel Unit 0xDB--DPLL Phase Detector Init (DPLL_PINI) 7 6 5 4 DPLL_PINI[7:0] 3 2 1 0 DPLL_PINI[7:0] DPLL Phase Detector Init (optional for RS8953B)--Phase detector init mode [PHD_MODE in CMD_7; addr 0xF4] selects whether DPLL_PINI is supplied by the MPU or is calculated automatically. When MPU supplied, DPLL_PINI sets the initial point within the phase comparator window that the phase detector returns to after detection of a DPLL error. The RS8953B phase window is 1,024 GCLK cycles. For example, the RS8953B requires a programmed value for DPLL_PINI which is typically set to init phase window at its center point (i.e., 512 GCLK cycles) from the following formula: 512 x BCLK DPLL_PINI = round -----------------------------4 x GCLK NOTE: The loaded value is internally multiplied by 4 when used to initialize the phase detector. 0xF6--Reset DPLL Phase Detector (DPLL_RST) Writing any data value to DPLL_RST clears the phase detector error output, restarts the phase comparator window, and clears pending DPLL error interrupts. The MPU is not required to write DPLL_RST, unless the MPU has instructed the Phase Detector Init Mode [PHD_MODE in CMD_7; addr 0xF4] to disable automatic initialization, or unless FAST_ACQ in CMD_7 is enabled and the system needs to reacquire the DPLL frequency. 4-38 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.10 Data Path Options 4.10 Data Path Options Table 4-7. Data Path Options Write Registers Address 0xDC 0xDD 0xDE 0xEA 0xE4 0xED 0xEE 0xF2 Register Label DBANK_1 DBANK_2 DBANK_3 FILL_PATT TSTUFF ROUTE_TBL COMBINE_TBL RSIG_TBL Bits 8 8 8 8 4 7 6 4 Data Bank Pattern 1 Data Bank Pattern 2 Data Bank Pattern 3 Name/Description Programmable Fill Pattern (Data Bank Pattern 4) Transmit Stuff Bit Value Transmit Routing Table Receive Combination Table Receive Signaling Table 0xDC--Data Bank Pattern 1 (DBANK_1) 7 6 5 4 DBANK_1[7:0] 3 2 1 0 DBANK_1[7:0] Data Bank Pattern 1--Holds an 8-bit programmable pattern that can be used to replace transmit HDSL payload bytes and/or receive PCM timeslots according to the Transmit Payload Map [TMAP; addr 0x08] and the Receive Combination Table [COMBINE_TBL; addr 0xEE] selections. Both transmit and receive can simultaneously use the same DBANK contents. DBANK_1[0] is the first bit inserted in the selected direction. The following configuration can cause the HDSL frame to become corrupted: DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte 33. TFIFO or DBank_1 is the source of data for HDSL payload byte 0. The LSB or the DBank_1 pattern is equal to one (1). 0xDD--Data Bank Pattern 2 (DBANK_2) 7 6 5 4 DBANK_2[7:0] 3 2 1 0 DBANK_2[7:0] Data Bank Pattern 2--Provides another 8-bit pattern for insertion in transmit HDSL payload bytes or receive PCM timeslots. See DBANK_1 above. Multiple DBANK registers may be needed to fill transmit HDSL payload bytes reserved by ETSI standards for future applications. For example, ETSI specifies R and Y bytes within a 2E1 payload block that are currently set to all 1s. N8953BDSB Conexant 4-39 4.0 Registers 4.10 Data Path Options RS8953B/8953SPB HDSL Channel Unit The following configuration can cause the HDSL frame to become corrupted: DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte 33. DBank_2 is the source of data for HDSL payload byte 0. The LSB of the DBank_2 pattern is equal to one (1). 0xDE--Data Bank Pattern 3 (DBANK_3) 7 6 5 4 DBANK_3[7:0] 3 2 1 0 DBANK_3[7:0] Data Bank Pattern 3--Holds a third possible 8-bit pattern for transmit or receive insertion. See DBANK_1 above. If RSIG_EN = 1 [CMD_6; addr 0xF3], DBANK_3 is a receive signaling buffer and is not available as an alternate source for receive PCM timeslots. If TAUX_EN = 1 [TCMD_2; addr 0x07], DBANK_3 is a transmit auxiliary channel data buffer and is not available for insertion into transmit HDSL payload bytes but remains available for insertion into RSER timeslots. The following configuration can cause the HDSL frame to become corrupted: DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte 33. DBank_3 is the source of data for HDSL payload byte 0. The LSB or the DBank_3 pattern is equal to one (1). 0xEA--Fill Pattern (FILL_PATT) 7 6 5 4 FILL_PATT[7:0] 3 2 1 0 FILL_PATT[7:0] Fill Pattern--When PRBS_DIS [CMD_3; addr 0xE7] is set, FILL_PATT replaces the PRBS generator output with its 8-bit programmable pattern. The transmit Routing Table [ROUTE_TBL; addr 0xED] may then select FILL_PATT as a fourth possible data bank to fill idle or unpopulated PCM timeslots and HDSL payload bytes. In this case, FILL_PATT also establishes an 8-bit pattern checked by the receiver's BER meter when enabled [BER_EN in COMBINE_TBL; addr 0xEE]. When PRBS_DIS is zero (PRBS enabled), FILL_PATT is used to initialize the least significant byte of the PRBS generator's LFSR. In this case, FILL_PATT must be initialized to any non-zero value before the MPU issues the PRBS_RST command. 0xE4--Transmit Stuff Bit Value (TSTUFF) 7 -- 6 -- 5 -- 4 -- MAG1 3 2 TSTUFF[3:0] SIGN1 MAG0 SIGNO 1 0 TSTUFF[3:0] Transmit Stuffing Bits--Contains the 4-bit STUFF value used by all HDSL transmitters when any HDSL output frame contains bit stuffing. TSTUFF[0] is the sign bit and first bit of the first quat transmitted during STUFF words. 4-40 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.10 Data Path Options 0xED--Transmit Routing Table (ROUTE_TBL) MPU access to the transmit routing table's single (ROUTE_TBL) register is enabled by first setting ROUTE_EN [CMD_3; addr 0xE7] to reset the table pointer. The MPU can then write up to 64 table entries sequentially to the ROUTE_TBL address. The RS8953B increments the internal table pointer after each write to ROUTE_TBL. Any writes beyond 64 will wrap around and overwrite the initial table entries. The first table entry written corresponds to the first transmit PCM timeslot, which is the 8-bit period starting at MSYNC's rising edge. Subsequent table writes increment the table pointer towards successive PCM timeslots. Standard E1 requires 32 table writes, corresponding to 32 timeslots. Standard T1 requires 25 table writes, where the F-bit location is treated as the 25th timeslot. An Nx64 transmit PCM channel may require up to 64 table writes, corresponding to the 4.096 Mbit/s data rate. After the MPU writes the required number of table entries, the MPU writes zero to ROUTE_EN to prevent further table access, and then write TFIFO_RST [addr 0x0D] on every HDSL channel to realign the transmit elastic stores if the aggregate HDSL data rate is modified. Subsequent table changes can rewrite only the necessary entries up to and including the last desired modification. 7 -- 6 INSERT_EN 5 ROUTE[1:0] CH3 4 3 ROUTE[1:0] CH2 2 1 ROUTE[1:0] CH1 0 ROUTE[1:0] Routing Code--Three identical routing codes are present in each table entry to select which data source is routed to each one of three HDSL channel destinations (CH1-CH3). Route data is available from three sources: PCM Transmit Serial data (TSER), PCM Insert Serial Data (INSDAT), and PRBS generator data. In addition, TSER data is available from an 8-bit delay buffer to allow routing codes to repeatedly (twice) use the same TSER byte as a data source. PCM timeslot data can also be discarded by selecting no destination channels. Note that INSDAT is available only from the 8-bit delay buffer, and cannot be repeated in the same manner as TSER. INSDAT occupies delay buffer space and prevents routing of previous TSER data during the timeslot following INSERT_EN. For example, if INSERT_EN is active in the timeslot 1 table entry, then during timeslot 2, the delay buffer contains INSDAT, and not the previous TSER. The PRBS generator is active only during timeslots that select PRBS data which allows discontinuous timeslots to be tested with a single continuous PRBS test pattern. Sequential timeslot routing is performed from inputs to destination channel(s) without reordering of timeslots. Figure 4-1 illustrates the effect of ROUTE[1:0] and INSERT_EN on TSER, INSDAT, and PRBS data routing. ROUTE[1:0] 00 01 10 11 Source of Transmit HDSL Channel Data Discard, do not route timeslot data TSER PRBS (or FILL_PATT, if PRBS_DIS = 1) Previous TSER (or INSDAT) from delay buffer Figure 4-1. Transmit Routing TSER INSDAT PRBS Delay 8 TFIFO1 TFIFO2 TFIFO3 INSERT_EN ROUTE[1:0] Ch. 1, 2, 3 N8953BDSB Conexant 4-41 4.0 Registers 4.10 Data Path Options INSERT_EN RS8953B/8953SPB HDSL Channel Unit Enable INSERT--Controls the state of the internal MUX and the INSERT output pin during the corresponding PCM timeslot's sample time. The next table entry is programmed to select the previous timeslot (ROUTE = 11) and to place INSDAT data from the previous timeslot into the TFIFO. 0 = INSERT output pin remains inactive (low) 1 = INSERT output pin active (high) 0xEE--Receive Combination Table (COMBINE_TBL) MPU access to the Receive Combination Table's (COMBINE_TBL) single register is enabled by writing COMB_EN [CMD_3; addr 0xE7], and by writing a maximum of 64 table entries sequentially to COMBINE_TBL. Each write increments the table pointer, and the first write corresponds to the first receive PCM timeslot. Subsequent writes increment the table pointer to successive timeslots. After writing the required number of table entries (see ROUTE_TBL), the MPU writes COMB_EN to disable table access, and then writes RFIFO_RST [addr 0x62] on every HDSL channel to realign the receive elastic stores. The MPU possibly writes RX_RST [addr 0xF1] if the aggregate PCM data rate has been modified. Subsequent table changes can rewrite entries only up to and including the last desired modification. 7 -- 6 -- 5 DBANK_SEL 4 3 DROP_EN 2 BER_EN 1 COMBINE[1:0] 0 COMBINE[1:0] Combine Code--Selects one of four data sources for output on RSER during the respective receive PCM timeslot destination. The data source is selected from one of three HDSL receive channels or the DBANK register. The first combine code that selects data from a HDSL channel will receive the first payload byte mapped from that channel's payload block, as determined by the payload map [RMAP; addr 0x64]. Whenever combine [1:0] is not 00, DBANK_SEL[1:0] must be 00. COMBINE[1:0] 00 01 10 11 Source of RSER Data Determined by DBANK_SEL[1:0] HDSL receive channel 1 HDSL receive channel 2 HDSL receive channel 3 BER_EN BER Meter Enable--Places a copy of the respective PCM timeslot's data into the BER meter. Any number of timeslots may be copied without affecting throughput. 0 = BER Meter ignores PCM timeslot 1 = BER Meter receives copy of PCM timeslot data from RSER DROP_EN Enable DROP--Controls the state of the DROP output pin which marks the respective timeslot coincident with data output on RSER. 0 = DROP output pin remains inactive (low) 1 = DROP output pin active (high) 4-42 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit DBANK_SEL[1:0] 4.0 Registers 4.10 Data Path Options Data Bank Select (Applicable only if COMBINE = 00)--Selects one of three DBANK registers to output on RSER during the respective timeslot. DBANK_SEL[1:0] 00 01 10 11 RSIG_EN 0 1 Source of RSER Output Data Determined by COMBINE[1:0] DBANK_1; addr 0xDC DBANK_2; addr 0xDD Determined by RSIG_EN RSER Source DBANK_3; addr 0xDE RSIG_TBL; addr 0xF2 0xF2--Receive Signaling Table (RSIG_TBL) Applicable only to the LTU grooming site in a 2E1 or 3E1 Point-to-Multipoint (P2MP) system, the receive signaling table assembles E1 Timeslot 16 (TS16) from the ABCD signaling supplied by the three remote sites. Signaling from each channel is located by RSIG_TBL selection of a particular timeslot in the receive combination table, and automatically sampled when RSIG_EN [CMD_6; addr 0xF3] is active. The groomed signaling table output replaces the DBANK_3 register selection in the receive Combination Table [COMBINE_TBL; addr 0xEE]. MPU access to the receive signaling table is provided through the RSIG_TBL register by first setting RSIG_WR [CMD_3; addr 0xE7] to reset the table pointer to zero, and then by writing up to 16 entries sequentially to RSIG_TBL. The RS8953B increments the table pointer after each write cycle to the RSIG_TBL address. The first table entry corresponds to the first E1 frame (frame 0) output on RSER and corresponds to subsequent entries to successive frames. Each entry contains two identical RSIG[1:0] grooming codes which select the HDSL channel source for ABCD signaling bits during the respective frame. For example, frame 1 grooming codes select ABCD for E1 channels 1 and 17, frame 2 selects ABCD for E1 channels 2 and 18, and so on. Grooming codes for E1 frame 0 are similar to other E1 frames, and allow the system to select which HDSL channel supplies the CAS Multiframe Alignment Signal (MAS) and which channel supplies the extra and multiframe yellow alarm bits (XYXX). RS8953B does not provide access to the actual received TS16 data and assumes that EOC messages or indicator bits are used to report far-end alarm and status information. 7 -- 6 -- 5 -- 4 -- 3 RSIG[1:0] 2 1 RSIG[1:0] 0 RSIG[1:0] Receive Signaling Grooming Code--Selects which HDSL channel supplies ABCD signaling, MAS, or XYXX bits for output on RSER during the PCM timeslot selected by receive combination table. Sixteen table entries correspond to E1 frames 0 through 15, where the most significant grooming code corresponds to the first four bits of the TS16 output. RSIG[1:0] 00 01 10 11 TS16 Source None (invalid) HDSL Channel 1 HDSL Channel 2 HDSL Channel 3 N8953BDSB Conexant 4-43 4.0 Registers 4.11 Common Command RS8953B/8953SPB HDSL Channel Unit 4.11 Common Command Table 4-8. Common Command Write Registers Address 0xE5 0xE6 0xE7 0xE8 0xE9 0xF3 0xF4 Register Label CMD_1 CMD_2 CMD_3 CMD_4 CMD_5 CMD_6 CMD_7 Bits 8 8 8 8 8 8 7 Name/Description Configuration Configuration Configuration Configuration Configuration Configuration Configuration 0xE5--Command Register 1 (CMD_1) 7 E1_MODE 6 PLL_DIS 5 PLL_DIV[1:0] 4 3 2 PLL_MUL[3:0] 1 0 PLL_MUL[3:0] PLL Multiplication Factor--The MCLK input frequency is multiplied from 1 to 16 times by the selected value to create an internal HFCLK approximately equal to 70 MHz and in the range of 60 to 80 MHz for DPLL clock recovery. When PLL_MUL has a value of 0xF, the PLL output is invalid. PLL_MUL [hex] MCLK Multiplier 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 8 9 7 A 6 B 5 C 4 D 3 E 2 F - PLL_DIV[1:0] PLL Division Factor--Selects a divisor to scale down the internal HFCLK frequency to create a General Purpose Clock (GCLK) in the frequency range of 10-15 MHz. PLL_DIV determines the GCLK frequency for the DPLL phase detector and loop filter. PLL_DIV 00 01 10 11 HFCLK Divisor 2 4 6 8 PLL_DIS PLL Disable--Disables the internal PLL which normally generates HFCLK. When disabled, a 60 to 80 MHz HFCLK must be applied externally on the MCLK input. 0 = Normal PLL operation 1 = Disable PLL (PLL_MUL value has no effect) E1_MODE E1 or Nx64 Mode--Enables insertion of Z-bits from the TZBIT [addr 0x04] registers, and extraction of Z-bits into the RZBIT [addr 0x04] registers. Otherwise, F-bits occupy the first bit of HDSL payload blocks. 0 = HDSL payload includes F-bits (T1 mode) 1 = HDSL payload includes Z-bits (E1 mode) 4-44 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.11 Common Command 0xE6--Command Register 2 (CMD_2) 7 GCLK_SEL 6 PCM_FLOAT 5 HP_LOOP 4 PP_LOOP 3 RCLK_SEL[1:0] 2 1 TCLK_SEL[1:0] 0 TCLK_SEL PCM Transmit Clock Source--Selects which clock source and clock edge are used for PCM transmit inputs and outputs. 00 01 1x TCLK (rising edge outputs, falling edge inputs) TCLK inverted (falling edge outputs, rising edge inputs) PCM receive clock source (see RCLK_SEL) RCLK_SEL PCM Receive Clock Source--Selects which clock source and which clock edge is used for PCM receive outputs. See also RCLK_INV [CMD_7; addr 0xF4]. 00 01 10 11 NOTE: DPLL recovered clock (rising edge outputs) EXCLK pin (rising edge outputs) EXCLK pin inverted (falling edge outputs) PCM transmit clock source (see TCLK_SEL) TCLK_SEL = 1x and RCLK_SEL = 11; both must not be set simultaneously. PP_LOOP Loopback Towards PCM on the PCM Side--The RSER and RMSYNC outputs are connected from TSER and TMSYNC inputs. Signals are switched directly at the I/O pins, without switching the PCM receive clock. The MPU must change RCLK_SEL to source RCLK from the TCLK input. HDSL transmit and receive channels operate normally, except the receive channel outputs are replaced by loopback signals. 0 = Normal PCM receive 1 = RSER and RMSYNC supplied by PCM transmit inputs HP_LOOP Loopback Towards HDSL on the PCM Side--The TSER and TMSYNC inputs are replaced by data and multiframe sync generated from the PCM receive formatter, without switching the PCM transmit clock. The MPU must change TCLK_SEL to source TCLK from the RCLK output. The PCM receiver operates normally, but the transmit TSER and TMSYNC inputs are ignored. 0 = Normal PCM transmit operation 1 = Transmit PCM data supplied by PCM receiver channel NOTE: PP_LOOP and HP_LOOP cannot be activated simultaneously. PCM_FLOAT Float PCM Multiframes--Selects whether MSYNC accepts TMSYNC as a frame and/or multiframe sync reference. MSYNC is always used to establish transmit frame and multiframe alignment for PCM and HDSL frames. If PCM_FLOAT is active, MSYNC ignores TMSYNC and allows unframed or asynchronous payload mapping of PCM frames into HDSL frames. In this case, TFRAME_LOC and TMF_LOC [addr 0xC0-0xC2] are also ignored. When PCM_FLOAT is zero, the TMSYNC input acts as the frame and/or multiframe sync reference for MSYNC. 0 = MSYNC accepts TMSYNC as transmit sync reference 1 = MSYNC ignores TMSYNC GCLK_SEL General Purpose Clock Source--Synchronizes MPU bus cycles and quantizes DPLL phase error. 0 = GCLK supplied by HFCLK / PLL_DIV 1 = GCLK supplied by TCK pin N8953BDSB Conexant 4-45 4.0 Registers 4.11 Common Command RS8953B/8953SPB HDSL Channel Unit 0xE7--Command Register 3 (CMD_3) 7 RSIG_WR 6 5 4 BER_SCALE[1:0] 3 2 PRBS_DIS 1 ROUTE_EN 0 COMB_EN PRBS_MODE[1:0] COMB_EN Enable Receive Combination Table Access--The write pointer for the combination table [COMBINE_TBL; addr 0xEE] is reset to 0, and table access is enabled. MPU writes to COMBINE_TBL are ignored when COMB_EN is low. 0 = Disable access to COMBINE_TBL 1 = Enable MPU access to COMBINE_TBL and reset write pointer ROUTE_EN Enable Transmit Routing Table Access--The write pointer for the transmit routing table [ROUTE_TBL; addr 0xED] is reset to 0, and table access is enabled. MPU writes to ROUTE_TBL are ignored when ROUTE_EN is low. 0 = Disable access to ROUTE_TBL 1 = Enable MPU access to ROUTE_TBL and reset write pointer PRBS_DIS PRBS Disable--Replaces PRBS generator output with data from the Fill Pattern Register [FILL_PATT; addr 0xEA]. Fill patterns are routed to the transmit FIFO in the same manner as PRBS patterns. 0 = PRBS generator output enabled 1 = Fill Pattern replaces PRBS data BER_SCALE[1:0] BER Meter Scale--Selects the test interval over which bit errors are accumulated by the BER Meter [BER_METER; addr 0x1D]. The test interval is counted only during bits selected and checked by the BER meter. See also BER_SEL [CMD_6; addr 0xF3]. BER_SCALE 00 01 10 11 NOTE: Test Interval 2 bits 228 bits 225 bits 221 bits 31 Approximate Scale 2 x 109 2 x 108 3 x 107 2 x 106 The time to complete the test interval depends on the number of bytes examined in each frame, where total test time may exceed 9 hours and 19 minutes. PRBS_MODE[1:0] Pseudo-Random Bit Sequence Length--Establishes the LFSR pattern generated by the transmit PRBS generator and checked by the receive BER meter. There is an inverter in the data path when the 215 test pattern is selected. PRBS_MODE 00 01 10 11 Test Pattern 2 23 LFSR Tap Selection 1 + x18 + x23 1 + x17 + x20 1 + x14 + x15 1 + x3 + x4 220 (14-zero limit) 215 24 RSIG_WR Enable Receive Signaling Table Access--The write pointer for the Receive Signaling Table [RSIG_TBL; addr 0xF2] is reset to 0, and table access is enabled. MPU writes to RSIG_TBL are ignored when RSIG_WR is low. 0 = Disable access to RSIG_TBL 1 = Enable MPU access to RSIG_TBL and reset write pointer 4-46 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.11 Common Command 0xE8--Command Register 4 (CMD_4) Must be set to 0x04 before any other MPU access to device, for normal operation. Other values are reserved for Conexant production test. 0xE9--Command Register 5 (CMD_5) 7 DPLL_NCO 6 5 4 ZBIT_SEL[1:0] 3 2 EXT_STUFF 1 STUFF_SEL[1:0] 0 MASTER_SEL[1:0] STUFF_SEL[1:0] Master STUFF source is applicable only if SLV_STUF [TCMD_2; addr 0x07] is enabled. The slave's bit stuffing is provided by the master STUFF source. STUFF_SEL[1:0] 00 01 10 11 NOTE: STUFF Source EXT_ STUFF (see below) HDSL Transmit Channel 1 HDSL Transmit Channel 2 HDSL Transmit Channel 3 If SLV_STUF is enabled and is also selected as master, then the master STUFF source automatically inserts 0 and 4 STUFF bits in alternating frames. EXT_STUFF External STUFF--Controls whether 0 or 4 STUFF bits are inserted for slave channels that select external stuffing. TSTUFF [addr 0xE4] supplies 4 STUFF bit values. The MPU must write EXT_STUFF at each slave's transmit frame interrupt. 0 = Insert 0 STUFF bits 1 = Insert 4 STUFF bits ZBIT_SEL[1:0] Z-bit Monitor Selection--Applicable only in E1 mode. ZBIT_SEL selects which channel supplies the last 40 Z-bits to fill the RZBIT_2-RZBIT_6 registers [addr 0x18-0x1C]. ZBIT_SEL[1:0] 00, 01 10 11 Monitor RZBIT[47:8] from HDSL receive channel 1 HDSL receive channel 2 HDSL receive channel 3 MASTER_SEL[1:0] Master Channel Selection--Selects which HDSL receive channel provides the 6 ms frame sync signal to the DPLL and PCM formatter. The selected channel's 6 ms frame is used to align the PCM receive timebase and to recover the PCM receive clock. MASTER_SEL[1:0] 00, 01 10 11 Master HDSL Receive Channel Channel 1 Channel 2 Channel 3 DPLL_NCO Operates the DPLL as an NCO --The DPLL operates in open loop configuration. Normally, the DPLL operates in closed loop to recover the PCM receive clock from the master HDSL receive channel. However, the DPLL may be operated in open loop as a Numerically Controlled Oscillator (NCO) when the master HDSL reference is unavailable (i.e., during startup procedure or loss of signal conditions). This bit is only monitored when DPLL is not in lock. 0 = Closed loop DPLL operation 1 = Open loop DPLL operation N8953BDSB Conexant 4-47 4.0 Registers 4.11 Common Command RS8953B/8953SPB HDSL Channel Unit 0xF3--Command Register 6 (CMD_6) 7 6 RAZ_[1:3] 5 4 RAUX_EN 3 RSIG_EN 2 MSYNC_MEAS 1 BER_SEL[1:0] 0 BER_SEL[1:0] BER/PRBS Mode--Selects the BER meter source, the PRBS generator output direction, and serial or framed data formats. Refer to Figure 3-12. BER_SEL 00 01 10 Mode Description PRBS outputs data under control of ROUTE_TBL. BER monitors data selected by COMBINE_TBL. Reserved -- PCM Framed PRBS outputs data under control of ROUTE_TBL. BER monitors TSER during the same timeslots selected by ROUTE_TBL. TCLK and RCLK must be identical. If accompanied by loopback on HDSL side, framed PCM channels are tested. PCM Serial PRBS output replaces RSER data. BER monitors all data at TSER. TCLK and RCLK must be identical. Mode Normal 11 MSYNC_MEAS MSYNC Phase Measurement--Selects whether TMSYNC or RMSYNC phase is measured with respect to MSYNC. The result is reported in MSYNC_PHS [addr 0x39]. 0 = TMSYNC to MSYNC phase measurement 1 = RMSYNC to MSYNC phase measurement RSIG_EN Receive Signaling Table Enable--Applicable only for an LTU in a P2MP application. When active, the Receive Signaling Table [RSIG_TBL; addr 0xF2] grooms the ABCD signaling from two or three remote sites and routes the groomed signal via DBANK_3 in the receive Combination Table [COMBINE_TBL; addr 0xEE]. When inactive, RSIG_TBL is unused and the receive combination table regains use of DBANK_3. 0 = Normal receive 1 = Enable receive signaling table RAUX_EN Receive Auxiliary Enable--The RAUX1-RAUX3 outputs share the same pins with DROP, INSERT, and MSYNC, respectively. RAUX_EN determines which signals are output on these shared pins. 0 = DROP, INSERT, or MSYNC outputs enabled 1 = RAUXn outputs enabled RAZ_1-RAZ_3 Receive Auxiliary Z-bit Enable--Applicable only when RAUX_EN is active. RAZn (n = 1,2,3) selects whether ROHn marks the output of all overhead and Z-bits or the output of only the last 40 Z-bits. If enabled, ROHn is high for one BCLKn, coincident with each of the last 40 Z-bits output on RAUXn. Otherwise, all data passed into the RFIFO is marked high by ROHn. 0 = ROHn marks all non-payload data 1 = ROHn marks only the last 40 Z-bits 4-48 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.11 Common Command 0xF4--Command Register 7 (CMD_7) 7 PRA_EN 6 FEBE_POLARITY 5 NCO_SCALE 4 RCLK_INV 3 PHD_MODE 2 1 FAST_ACQ 0 DPLL_ERR_EN DPLL_ERR_EN DPLL Error Interrupt Enable--Enables DPLL errors to request RX_ERR interrupt when an overflow or underflow condition occurs at the phase detector output. DPLL errors are latched and reported in ERR_STATUS [addr 0x3C] regardless of DPLL_ERR_EN. 0 = DPLL errors do not generate a RX_ERR interrupt 1 = DPLL errors generate a RX_ERR interrupt FAST_ACQ Fast Acquisition--Enables DPLL fast frequency acquisition by instructing the NCO to reuse the residual phase calculated prior to a DPLL error condition. The phase detector initializes according to PHD_MODE (see below) while the NCO continues tracking the last known phase, thus widening the DPLL bandwidth. FAST_ACQ is preferable while the master framer remains IN_SYNC. To avoid RCLK frequency violations, FAST_ACQ may be disabled when the master framer is OUT_OF_SYNC. 0 = Disable fast acquisition 1 = Enable fast acquisition NOTE: If the system determines that the DPLL is not locked, then the MPU must assert DPLL _RST [addr 0xF6] to force the DPLL to reload DPLL_RSID [addr 0xD5]. The system may monitor DPLL tracking by reading RESID_OUT [addr 0x28] or by checking DPLL_ERR [ERR_STATUS; addr 0x3C]. PHD_MODE Phase Detector Init Mode--Selects a method to initialize the phase detector window when a DPLL error occurs. The phase detector can either initialize to the center of the phase window or opposing edge, not initialize at all, or use the programmed DPLL_PINI [addr 0xDB] value. PHD_MODE 00 01 10 11 NOTE: Phase Detector Initialization DPLL_PINI value Opposing edge of phase window Disabled (infinite phase window) Center of phase window Disabling the phase detector is not recommended as the error output can remain saturated without reporting the DPLL error status or generating DPLL interrupts. RCLK_INV Receive Output Clock Inverted--Enables binary inversion of the clock selected by RCLK_SEL [CMD_2; addr 0xE6]. 0 1 RCLK = Clock selected by RCLK_SEL RCLK = Inverted clock selected by RCLK_SEL N8953BDSB Conexant 4-49 4.0 Registers 4.11 Common Command NCO_SCALE RS8953B/8953SPB HDSL Channel Unit NCO Scale Factor--Divides the NCO clock by 4 to allow the NCO to synthesize the RCLK frequency at or below 128 kHz. GCLK and SCLK are not affected. 0 = Normal NCO operation 1 = Divide NCO clock (HFCLK) by 4 NOTE: Calculated values for DPLL_RESID [addr 0xD5] and DPLL_FACTOR [addr 0xD7] are changed according to the following equation: f MCLK x PLL_MUL [INTEGER.FRACTION] = ------------------------------------------------ 4 x 2 x f PCM FEBE_POLARITY Determines the value of the FEBE bit that increments the FEBE counter. 0 = FEBE counter increments when FEBE bit is high 1 = FEBE counter increments when FEBE bit is low PRA_EN Enable or globally disable the PRA circuitry. 0 = Disable ALL PRA functionality 1 = Enable ALL PRA functionality 4-50 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.12 Interrupt and Reset 4.12 Interrupt and Reset Table 4-9. Interrupt and Reset Write Registers Address 0xEB 0xEC 0xEF 0xF0 0xF1 Register Label IMR ICR BER_RST PRBS_RST RX_RST Bits 8 8 -- -- -- Interrupt Mask Register Interrupt Clear Register Name/Description Reset BER Meter/Start BER Measurement Reset PRBS Generator Reset Receiver 0xEB--Interrupt Mask Register (IMR) The MPU writes a 1 to an IMR bit to mask the respective interrupt event. Masked interrupt sources are prevented from generating an active low signal on the INTR* output, but are reported in the Interrupt Request Register (IRR). Writing zero to the IMR bit enables the respective interrupt event to generate an active low signal on the INTR* output. Upon power-up or RST* assertion, all IMR bits are automatically set to 1 to disable the INTR* output. 7 RX_ERR 6 TX_ERR 5 4 RX[3:1] 3 2 1 TX[3:1] 0 TX1-TX3 RX1-RX3 TX_ERR RX_ERR Mask the HDSL 6 ms transmit frame interrupt for the respective channel. Mask the HDSL 6 ms receive frame interrupt for the respective channel. Mask the HDSL transmit error interrupt. Mask the HDSL receive error interrupt. 0xEC--Interrupt Clear Register (ICR) The MPU writes a zero to an ICR bit to reset the respective IRR bit and, if all IRR bits are 0, causes the INTR* output to enter a high impedance state. Writing a 1 has no effect. 7 RX_ERR 6 TX_ERR 5 4 RX[3:1] 3 2 1 TX[3:1] 0 TX1-TX3 RX1-RX3 TX_ERR RX_ERR Clear the HDSL 6 ms transmit frame interrupt for the respective channel. Clear the HDSL 6 ms receive frame interrupt for the respective channel. Clear the HDSL transmit error interrupt. Clear the HDSL receive error interrupt. N8953BDSB Conexant 4-51 4.0 Registers 4.12 Interrupt and Reset RS8953B/8953SPB HDSL Channel Unit 0xEF--Reset BER Meter/Start BER Measurement (BER_RST) Writing any data value to BER_RST clears the BER Meter error count [BER_METER; addr 0x1D]. The BER Meter Status [BER_STATUS; addr 0x1E] instructs the BER meter to begin searching for pattern sync according to the mode selected by PRBS_MODE [CMD_3; addr 0xE7] and BER_SEL [CMD_6; addr 0xF3]. It restarts the BER meter test measurement interval defined by BER_SCALE [CMD_3; addr 0xE7]. The MPU must configure PRBS_MODE, BER_SEL and BER_SCALE before issuing a BER_RST command. After writing BER_RST, the MPU monitors SYNC_DONE to determine when the test pattern qualification period has ended and then checks BER_SYNC [BER_STATUS; addr 0x1E] to verify that correct test pattern has been received. The BER meter uses a 128-bit qualification period to examine receive data before updating BER_SYNC, therefore the MPU may wait up to 2 ms before SYNC_DONE is activated. If BER_SYNC is not found when the qualification period ends, then the test has failed to detect pattern sync and the MPU should ignores the BER_METER results. The MPU may optionally repeat BER_RST in the event of a PRBS test failure since the BER meter may have initialized LFSR with received bit errors. Similarly, the MPU should repeat BER_RST if BER_METER reports any bit errors at the end of the qualification period during a PRBS test. Once BER_SYNC is detected, the MPU monitors BER_DONE to determine the end of the test measurement interval. BER_METER results are updated in real time during the measurement interval and latched at the end of the interval. The MPU can restart the test measurement interval and thereby extend the measurement indefinitely by applying another BER_RST command before BER_DONE is activated. 0xF0--Reset PRBS Generator (PRBS_RST) Writing any data value to PRBS_RST loads an 8-bit pattern from the FILL_PATT Register [addr 0xEA] into the least significant byte of the PRBS generator's 23-stage LFSR and clears all other LFSR bits. The MPU writes PRBS_RST prior to the start of a PRBS or fixed pattern test. NOTE: Before issuing PRBS_RST to start a PRBS test, the MPU must initialize the FILL_PATT value to something other than 0x00, or the LFSR output will be stuck at all 0s. 0xF1--Reset Receiver (RX_RST) For the RS8953B, writing any data value to RX_RST forces the PCM formatter to align the PCM receive timebase with respect to the master HDSL channel's receive 6 ms frame by reloading the RFIFO_WL value [addr 0xCD]. The MPU must write RX_RST after modifying the RFIFO_WL value in the RS8953B. The RS8953B automatically performs RX_RST each time the master HDSL channel's receive framer changes alignment and transitions to the IN_SYNC state. Issuing RX_RST while the PCM formatter is aligned causes no change in alignment of the PCM receive timebase. 4-52 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.13 Receive/Transmit Status 4.13 Receive/Transmit Status HDSL Channel 1 (CH1) Base Address 0x00 HDSL Channel 2 (CH2) 0x08 HDSL Channel 3 (CH3) 0x10 Table 4-10. Receive and Transmit Status Read Registers CH1 0x00 0x01 0x02 0x03 0x04 CH2 0x08 0x09 0x0A 0x0B 0x0C 0x18 0x19 0x1A 0x1B 0x1C CH3 0x10 0x11 0x12 0x13 0x14 Register Label REOC_LO REOC_HI RIND_LO RIND_HI RZBIT_1 RZBIT_2 RZBIT_3 RZBIT_4 RZBIT_5 RZBIT_6 Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Receive EOC Bits Receive EOC Bits Receive IND Bits Receive IND Bits Receive Z-bits Register Description Common Receive Z-bits (CHn = ZBIT_SEL) Common Receive Z-bits (CHn = ZBIT_SEL) Common Receive Z-bits (CHn = ZBIT_SEL) Common Receive Z-bits (CHn = ZBIT_SEL) Common Receive Z-bits (CHn = ZBIT_SEL) Receive Status Receive Status Transmit Status CRC Error Count Far-End Block Error Count 0x05 0x06 0x07 0x21 0x22 0x0D 0x0E 0x0F 0x29 0x2A 0x15 0x16 0x17 0x31 0x32 STATUS_1 STATUS_2 STATUS_3 CRC_CNT FEBE_CNT The MPU may read all receive and transmit status registers non-destructively at any time. All status registers are updated coincident with their respective HDSL channel's receive or transmit 6 ms frame interrupts indicated in the Interrupt Request Register [IRR; addr 0x1F]. Therefore, the MPU may poll the IRR or enable interrupts to determine whether a status update has occurred. Real-time receive status (REOC, RIND, and RZBIT) register updates are suspended when the respective HDSL channel's receive framer reports an OUT_OF_SYNC state [STATUS_1; addr 0x05]. 0x00--Receive Embedded Operations Channel (REOC_LO) 7 6 5 4 REOC[7:0] 3 2 1 0 N8953BDSB Conexant 4-53 4.0 Registers 4.13 Receive/Transmit Status RS8953B/8953SPB HDSL Channel Unit 0x01--Receive Embedded Operations Channel (REOC_HI) 7 6 MFG[2:0] 5 4 3 2 RE0C[12:8] 1 0 REOC[12:0] Receive EOC--Holds 13 EOC bits received during the previous HDSL frame. Refer to Table 3-2 (Overhead Bit Allocation) for EOC bit positions within the frame. The LSB REOC[0] is received first. Manufacture Code--Contains the device manufacture ID code. CH1 (address 0x01) CH2 (address 0x09) CH3 (address 0x11) 001 010 100 MFG[2:0] 0x02--Receive Indicator Bits (RIND_LO) 7 6 5 4 RIND[7:0] 3 2 1 0 0x03--Receive Indicator Bits (RIND_HI) 7 6 MINOR_VER[2:0] 5 4 3 2 RIND[12:8] 1 0 RIND[12:0] Receive IND--Holds 13 IND bits received during the previous HDSL frame. Refer to Table 3-2 (Overhead Bit Allocation) for the IND bit positions within the frame. The receive framer updates the RIND registers on receive frame interrupt boundaries. The LSB RIND[0] is received first. Minor Version Number--Contains the device minor revision level which the MPU can read to determine the installed device, enabled new software features, and remove unnecessary software corrections from older versions. CH1 (address 0x03) CH2 (address 0x0B) CH3 (address 0x13) Rev A 000 010 000 Rev B 000 010 001 Rev C 000 010 010 MINOR_VER[2:0] 0x04--Receive Z-Bits (RZBIT_1) 7 6 5 4 RZBIT[7:0] 3 2 1 0 4-54 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.13 Receive/Transmit Status 0x18--Receive Z-Bits (RZBIT_2) 7 6 5 4 RZBIT[15:8] 3 2 1 0 0x19--Receive Z-Bits (RZBIT_3) 7 6 5 4 RZBIT[23:16] 3 2 1 0 0x1A--Receive Z-Bits (RZBIT_4) 7 6 5 4 RZBIT[31:24] 3 2 1 0 0x1B--Receive Z-Bits (RZBIT_5) 7 6 5 4 RZBIT[39:32] 3 2 1 0 0x1C--Receive Z-Bits (RZBIT_6) 7 6 5 4 RZBIT[47:40] 3 2 1 0 RZBIT[47:0] Receive Z-bits--Applicable only in E1_MODE [CMD_1; addr 0xE5]. RZBIT holds 48 Z-bits received during the previous HDSL frame. Refer to Figures 3-21 and 3-26 for Z-bit positions within the frame. The LSB RZBIT[0] is received first. The first 8 received Z-bits from each HDSL channel are individually monitored in the RZBIT_1 registers. The last 40 received Z-bits are monitored in the RZBIT_2-RZBIT_6 registers from only the single receive channel selected by ZBIT_SEL [CMD_5; addr 0xE9]. Systems which need individual channel monitoring of the last 40 Z-bits can use external circuitry to capture the Z-bits from the receive HDSL auxiliary channel (RAUXn) outputs. 0x05--Receive Status 1 (STATUS_1) 7 6 5 RFIFO_SLIP 4 RFIFO_MPTY 3 RFIFO_FULL 2 RX_STUFF 1 TR_INVERT 0 SYNC_AB MAJOR_VER[1:0] N8953BDSB Conexant 4-55 4.0 Registers 4.13 Receive/Transmit Status SYNC_AB RS8953B/8953SPB HDSL Channel Unit SYNC_WORD_A or SYNC_WORD_B Acquired--Reports which one of the two programmed SYNC words is detected by the receive framer. Updated each time the receive framer state transitions from OUT_OF_SYNC to SYNC_ACQUIRED. 0 = SYNC_ACQUIRED with SYNC_WORD_A 1 = SYNC_ACQUIRED with SYNC_WORD_B TR_INVERT Tip/Ring Inversion--Indicates the receive framer acquired an inverted SYNC word A or B, indicating that the receive tip and ring wire pair connections are reversed. The RS8953B automatically inverts the sign bits of all received data as it is presented on the RDATn input when inversion is detected. TR_INVERT is updated each time the receive framer state transitions from OUT_OF_SYNC to SYNC_ACQUIRED. 0 = SYNC_ACQUIRED with expected SYNC word 1 = SYNC_ACQUIRED with inverted SYNC word RX_STUFF Receive STUFF--Indicates whether the receive framer detected 4 STUFF bits or no STUFF bits in the previous frame. 0 = No STUFF bits detected 1 = 4 STUFF bits detected RFIFO_FULL Receive FIFO Full Error--Indicates the RFIFO has overflowed. Also reported in ERR_STATUS and IRR (if RX_ERR_EN in RCMD_2[addr0x61]), and generates an RX_ERR interrupt (if RX_ERR in IMR is enabled). RFIFO_FULL is indicative of clock problems and may be triggered by DPLL acquisition, DPLL switchover, or by changes to the receive combination table, or to the receive payload map. 0 = RFIFO normal 1 = RFIFO overflowed RFIFO_MPTY Receive FIFO Empty Error--Indicates the RFIFO has Underrun. Also reported in ERR_STATUS and IRR (if RX_ERR_EN in RCMD_2[addr0x61]), and generates an RX_ERR interrupt (if RX_ERR in IMR is enabled). RFIFO_MPTY is indicative of clock problems and may be triggered by events similar to those which cause RFIFO_FULL errors. 0 = RFIFO normal 1 = RFIFO Underrun RFIFO_SLIP Receive FIFO Slip--Indicates the number of payload bytes mapped into the RFIFO is not equal to the number of PCM timeslots mapped out of the RFIFO over a 6 ms period, also reported in ERR_STATUS and IRR (if RX_ERR_EN in RCMD_2[addr0x61]). It generates an RX_ERR interrupt (if RX_ERR in IMR is enabled). RFIFO_SLIP errors are caused by a receive framer OUT_OF_SYNC condition, or by improper configuration of the receive payload map, or the receive combination table. 0 = RFIFO normal 1 = RFIFO unbalanced MAJOR_VER[1:0] Major Version Number--Contains the device major revision level which the CPU can read to determine the installed device, enable new software features, and remove unnecessary software corrections from older versions. CH1 (address 0x05) CH2 (address 0x0D) CH3 (address 0x15) Bt8953 01 01 01 Bt8953A 01 01 10 RS8953B 01 01 11 4-56 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.13 Receive/Transmit Status 0x06--Receive Status 2 (STATUS_2) 7 FEBE_OVR 6 CRC_OVR 5 CRC_ERR 4 3 2 1 STATE_CNT[2:0] 0 SYNC_STATE[1:0] STATE_CNT[2:0] Intermediate State Count--Applicable only if SYNC_STATE reports SYNC_ACQUIRED or SYNC_ERRORED states. STATE_CNT indicates the framer's progress through the intermediate states. 000 001 010 011 100 101 110 111 1 Frame 2 Consecutive Frames 3 Consecutive Frames 4 Consecutive Frames 5 Consecutive Frames 6 Consecutive Frames 7 Consecutive Frames 8 Consecutive Frames SYNC_STATE[1:0] Receive Framer Synchronization State--Reports the state of the receive framer. Refer to the Framer Synchronization State Diagram (Figure 3-23). 00 01 10 11 OUT_OF_SYNC SYNC_ACQUIRED IN_SYNC SYNC_ERRORED When the framer enters OUT_OF_SYNC, the RFIFO is automatically reset, FEBE and CRC error counts are suspended, and RX_ERR is activated. When the framer reports SYNC_ACQUIRED, the RFIFO and the payload mapper are enabled, and RX_ERR is activated. When the framer enters IN_SYNC, the RFIFO Water Level [RFIFO_WL; addr 0xCD] is re-established, FEBE and CRC counting resumes, and RX_ERR is activated. When the framer reports SYNC_ERRORED, STATE_CNT indicates the number of consecutive frames in which SYNC was not detected. CRC_ERR CRC Error--Shows that the CRC comparison in the previous frame resulted in a mismatch of 1 or more CRC bits. CRC_ERR is invalid in the OUT_OF_SYNC state. The MPU may copy CRC_ERR into the first transmit IND [TIND_LO; addr 0x02] to report FEBE. 0 = CRC pass 1 = CRC error detected CRC_OVR CRC Error Count Overflow--Indicates the CRC Error Count [CRC_CNT; addr 0x21] has reached its maximum value of 255, and generates an RX_ERR interrupt. 0 = CRC error count below maximum 1 = CRC error count equals maximum 255 (0xFF) FEBE_OVR Far-End Block Error Count Overflow--Indicates the FEBE count [FEBE_CNT; addr 0x22] has reached its maximum value of 255. Generates an RX_ERR interrupt. 0 = FEBE count below maximum 1 = FEBE count equals maximum 255 (0xFF) N8953BDSB Conexant 4-57 4.0 Registers 4.13 Receive/Transmit Status RS8953B/8953SPB HDSL Channel Unit 0x07--Transmit Status (STATUS_3) 7 -- 6 -- 5 -- 4 STUFF_ERR 3 TFIFO_SLIP 2 TFIFO_MPTY 1 TFIFO_FULL 0 TX_STUFF TX_STUFF Transmit STUFF Decision--Indicates whether the last transmitted HDSL frame was output with 4 STUFF bits or none. 0 = No STUFF bits output 1 = 4 STUFF bits output TFIFO_FULL Transmit FIFO Full Error--Indicates the TFIFO has overflowed. This is also reported in ERR_STATUS and IRR (if TX_ERR_EN in TCMC_1[addr0x06]) and generates a TX_ERR interrupt (if TX_ERR in IMR is enabled). TFIFO_FULL errors may result from a change of transmit PCM frame alignment when MPU writes to TFIFO_RST, or from any changes in TCLK or BCLKn frequency or to the transmit routing table or the transmit payload map. 0 = TFIFO normal 1 = TFIFO overflowed TFIFO_MPTY Transmit FIFO Empty Error--Indicates the TFIFO has Underrun. This is also reported in ERR_STATUS and IRR (if TX_ERR_EN in TCMC_1[addr0x06]), and generates a TX_ERR interrupt (if TX_ERR in IMR is enabled). TFIFO_MPTY errors may be triggered by events similar to those which cause TFIFO_FULL errors. 0 = TFIFO normal 1 = TFIFO Underrun TFIFO_SLIP Transmit FIFO Slip--Indicates that the number of PCM timeslots routed into the TFIFO is not equal to the number of payload bytes mapped out of the TFIFO over a 6 ms period. This is also reported in ERR_STATUS and IRR (if TX_ERR_EN in TCMC_1[addr0x06]), and generates a TX_ERR interrupt (if TX_ERR in IMR is enabled). TFIFO_SLIP errors may be triggered by events similar to those which cause TFIFO_FULL errors. Repeated TFIFO_SLIP errors may indicate improper configuration of either the transmit payload map or the transmit routing table. 0 = Transmit FIFO normal 1 = Transmit FIFO unbalanced STUFF_ERR Transmit Stuffing Error--Indicates when the phase difference measured from PCM to HDSL 6 ms frames exceeds the maximum bit Stuffing Threshold [STF_THRESH_C; addr 0xD3]. This is also reported in ERR_STATUS and IRR (if TX_ERR_EN) and generates a TX_ERR interrupt (if TX_ERR in IMR is enabled). STUFF_ERR may be triggered by events similar to those which cause TFIFO_FULL errors. The STUFF generator is automatically reset when STUFF_ERR is detected. 0 = STUFF generator normal 1 = STUFF generator error 0x21--CRC Error Count (CRC_CNT) 7 6 5 4 CRC_CNT[7:0] 3 2 1 0 4-58 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit CRC_CNT[7:0] 4.0 Registers 4.13 Receive/Transmit Status CRC Error Count--Indicates the total number of received CRC errors detected by the receive framer, and increments by one for each received HDSL 6 ms frame that contains CRC_ERR [STATUS_1; addr 0x06]. CRC_CNT is cleared to 0 by ERR_RST [addr 0x67]. Error counting is suspended while the receive framer is OUT_OF_SYNC or SYNC_ACQUIRED. CRC_CNT also sets CRC_OVR [STATUS_2; addr 0x06] upon reaching its maximum count value of 255. 0x22--Far End Block Error Count (FEBE_CNT) 7 6 5 4 FEBE_CNT[7:0] 3 2 1 0 FEBE_CNT[7:0] Far-End Block Error Count--Indicates the total number of received FEBE errors sent by the far-end transmitter and increments by 1 for each received HDSL 6 ms frame that contains an active FEBE bit. The polarity of active FEBE is determined by FEBE_POLARITY in CMD_7 (addr 0xF4). FEBE is the second IND bit received within the indicator bit group and can be monitored separately as the RIND[1] bit in the RIND_LO [addr 0x02] receive status register. Refer to Table 3-2 for the FEBE bit position within the frame. FEBE_CNT is reset to 0 by ERR_RST [addr 0x67]. Error counting is suspended while the receive framer is OUT_OF_SYNC or SYNC_ACQUIRED. FEBE_CNT also sets FEBE_OVR [STATUS_2; addr 0x06] upon reaching its maximum count value of 255. N8953BDSB Conexant 4-59 4.0 Registers 4.14 Common Status RS8953B/8953SPB HDSL Channel Unit 4.14 Common Status Table 4-11. Common Status Read Registers Address 0x1D 0x1E 0x1F 0x20 0x28 0x30 0x38 0x39 0x3A 0x3B 0x3C Register Label BER_METER BER_STATUS IRR RESID_OUT_HI RESID_OUT_LO IMR PHS_ERR MSYNC_PHS_LO MSYNC_PHS_HI SHADOW_WR ERR_STATUS Bits 8 3 8 8 8 8 8 8 5 8 7 Name/Description Bit Error Rate Meter BER Meter Status Interrupt Request Register DPLL Residual DPLL Residual Interrupt Mask Register DPLL Phase Error Multiframe Sync Phase Multiframe Sync Phase Shadow Write Error Status 0x1D--Bit Error Rate Meter (BER_METER) The receive BER meter and the transmit PRBS generator work in conjunction to perform characterization, installation, maintenance, and diagnostic testing on PCM and HDSL channels. PRBS_MODE and PRBS_DIS [CMD_3; addr 0xE7] determine which of the four PRBS patterns or constant pattern is checked by the BER meter. 7 6 5 4 BER[7:0] 3 2 1 0 BER[7:0] Bit Error Ratio--Contains the total number of logical bit errors counted in real time during the test measurement interval defined by BER_SCALE [CMD_3; addr 0xE7]. BER stops counting when the test measurement interval is completed or the counter reaches its maximum value of 255, after which the BER_METER result is latched until the meter is reset [BER_RST; addr 0xEF]. NOTE: BER does not suspend error counting when the HDSL receive framer loses frame alignment. Any time after test completion [see BER_DONE in BER_STATUS; addr 0x1E], the MPU can calculate an exact Bit Error Ratio, as follows: BER_SCALE 00 01 10 11 Bit Error Ratio BER[7:0] / 231 BER[7:0] / 228 BER[7:0] / 225 BER[7:0] / 221 4-60 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.14 Common Status 0x1E--BER Status (BER_STATUS) 7 -- 6 -- 5 -- 4 -- 3 -- 2 SYNC_DONE 1 BER_DONE 0 BER_SYNC BER_SYNC BER Pattern SYNC--Applicable only if SYNC_DONE is active. BER_SYNC reports whether the BER meter acquired test pattern sync during the 128-bit test pattern qualification period. The BER meter must detect fewer than 8 bit errors during examination of the first 128 bits to assert BER_SYNC. BER_SYNC can report a false pattern sync if all 1s or all 0s are applied. 0 = No pattern sync 1 = Pattern sync detected BER_DONE BER Measurement Complete--Signifies the BER meter has completed examination of the total number of test pattern bits programmed by BER_SCALE. When BER_DONE is set, the BER meter stops counting bit errors. 0 = BER measurement in progress 1 = BER measurement complete SYNC_DONE Sync Qualification Period Complete--Indicates the BER meter has examined 128 bits and has updated BER_SYNC. SYNC_DONE reports the end of the test pattern qualification period. 0 = Qualification period in progress 1 = Qualification period complete 0x1F--Interrupt Request Register (IRR) The INTR* output pin is activated and the corresponding IRR bit latched whenever an interrupt event transition is detected from one of eight sources. Interrupt sources that are masked [see IMR; addr 0xEB] do not activate the INTR* output but are latched and reported in the IRR. Latched IRR bits are reset and the INTR* output is deactivated by writing a 0 to the corresponding Interrupt Clear Register bits [ICR; addr 0xEC]. However, if IRR is reporting a persistent error condition such as framer OUT_OF_SYNC, then writing ICR deactivates the INTR* pin, but does not clear the IRR bit unless the error condition has ended. INTR* output activation is triggered by an event edge; therefore, persistent or multiple error conditions only generate one INTR* request. 7 RX_ERR 6 TX_ERR 5 4 RX[3:1] 3 2 1 TX[3:1] 0 TX1-TX3 Transmit HDSL 6 ms Frame Interrupt--Reported coincident with the start of the transmit 6 ms frame for the respective HDSL channel. This allows the MPU to synchronize read access of the transmit status [STATUS_3; addr 0x07] and to synchronize write access to the real time transmit HDSL registers (see Table 4-2). 0 = No interrupt 1 = Transmit frame interrupt N8953BDSB Conexant 4-61 4.0 Registers 4.14 Common Status RX1-RX3 RS8953B/8953SPB HDSL Channel Unit Receive HDSL 6 ms Frame Interrupt--Reported coincident with the start of the receive 6 ms frame for the respective HDSL channel. This allows the MPU to synchronize read access of the real time receive status (see Table 4-10) and the DPLL status of the master HDSL receive channel (see Table 4-11). 0 = No interrupt 1 = Receive frame interrupt TX_ERR Transmit Error Interrupt--The transmit stuffing and TFIFO errors from all enabled error sources are logically ORed to form TX_ERR. When active, the MPU reads the Error Status Register [ERR_STATUS; addr 0x3C] to determine which source caused the interrupt. 0 = No interrupt 1 = Transmit error interrupt RX_ERR Receive Error Interrupt--Framer state transitions, RFIFO errors, CRC and FEBE counter overflows, and DPLL errors from all enabled error sources are logically ORed to form RX_ERR. When active, the MPU reads the Error Status Register [ERR_STATUS; addr 0x3C] to determine which source caused the interrupt. 0 = No interrupt 1 = Receive error interrupt 0x28--DPLL Residual Output (RESID_OUT_LO) 7 6 5 4 RESID_OUT[7:0] 3 2 1 0 0x20--DPLL Residual Output (RESID_OUT_HI) 7 6 5 4 3 2 1 0 RESID_OUT[15:8] RESID_OUT[15:0] DPLL Residual Output--The NCO's residual phase output equals the synthesized phase needed to construct half-cycle of the recovered clock, given as a fractional result, in units of HFCLK. During DPLL closed loop operation, the RESID_OUT value should converge to approximately equal the programmed DPLL_RESID [addr 0xD6] value. The MPU can calculate the recovered clock frequency by substituting the measured value of RESID_OUT in the synthesis equation, and solving for RCLK. RESID_OUT is updated coincident with the RXn interrupt (where n = master HDSL channel number) and is provided for diagnostics only. 0x30--Interrupt Mask Register (IMR) This register contains data written to IMR [addr 0xEB] and is provided as an MPU read back register. The MPU interrupt service routine can use the IMR read value to mask read data from the IRR and to avoid processing of masked interrupts. 4-62 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.14 Common Status 0x38--DPLL Phase Error (PHS_ERR) 7 6 5 4 PHS_ERR[7:0] 3 2 1 0 PHS_ERR[7:0] DPLL Phase Error--The DPLL phase detector error output is given in 2's complement format in units of GCLK cycles, where minimum (negative) phase is reported as 0x80 and maximum (positive) phase as 0x7F. The result of the PCM to HDSL 6 ms phase comparison is updated coincident with the RXn interrupt (where n = master HDSL channel number). During DPLL closed loop operation, the phase error's long term average equals zero. PHS_ERR is provided for diagnostic testing only. 0x39--Multiframe Sync Phase Low (MSYNC_PHS_LO) 7 6 5 4 3 2 1 0 MSYNC_PHS[7:0] 0x3A--Multiframe Sync Phase High (MSYNC_PHS_HI) 7 -- 6 -- 5 -- 4 3 2 MSYNC_PHS[12:8] 1 0 MSYNC_PHS[12:0] Multiframe Sync Phase--Contains the number of elapsed TCLK cycles measured from the rising edge of the TMSYNC or the RMSYNC signal selected by MSYNC_MEAS [CMD_6; addr 0xF3] to the rising edge of MSYNC. A value of zero indicates the phase equals 1 TCLK cycle. Maximum phase equals 1 PCM multiframe. For example, Nx64 multiframe equals 16 frames times [N = 64 the timeslots per frame, times 8 bits per timeslot, for a total length equal to 8,192 PCM bits (0x1FFF]. For unframed or asynchronously mapped applications, knowing the TMSYNC to MSYNC phase simplifies far-end reconstruction of RMSYNC. Therefore, each terminal measures TMSYNC phase, and sends it to the far-end for calculation of the RFRAME_LOC [addr 0xC3] and the RMF_LOC [addr 0xC5] delays needed to recreate RMSYNC. TMSYNC phase measurement is unnecessary when PCM and HDSL frames are synchronized or the far-end does not need to create RMSYNC. t ( TMP ) RMF_LOC.RFRAME_LOC = ---------------------------------FRAME_LEN where: FRAME_LEN = Bits per frame [FRAME_LEN; address 0xC8] RMF_LOC = Frame delay (integer part of result) RFRAME_LOC = Bit delay (fractional part of result) t(TMP) = TMSYNC to MSYNC Phase (in PCM bits) N8953BDSB Conexant 4-63 4.0 Registers 4.14 Common Status RS8953B/8953SPB HDSL Channel Unit The NTU in a P2MP application uses both measurements to monitor the phase difference between incoming and outgoing HDSL frames, to adjust its output frame location accordingly to align with other remote sites, and to communicate the resulting transmit frame offset to the LTU for grooming purposes. Refer to the Receive Signaling Location Register [RSIG_LOC; addr 0x68]. 0x3B--Shadow Write (SHADOW_WR) 7 6 5 4 WR[7:0] 3 2 1 0 WR[7:0] Most Recent Write Data--Contains the data latched during the last MPU write cycle to any location within the RS8953B address space. System diagnostics can read-verify the data written to validate MPU access over the address/data bus. 0x3C--Error Status (ERR_STATUS) ERR_STATUS is a read-clear register in RS8953B. Reading ERR_STATUS forces its contents to 0. Transmit and receive HDSL channel errors and DPLL errors are reported individually in ERR_STATUS, where they are indefinitely latched until cleared. The MPU reads ERR_STATUS to determine the cause of a TX_ERR or RX_ERR interrupt. Each source has independent Interrupt Error Enables (TX_ERR_EN, RX_ERR_EN and DPLL_ERR_EN), which prevent it from setting the corresponding IRR interrupt. See error interrupt enables in TCMD_1 [addr 0x06], RCMD_2 [addr 0x61], and CMD_7 [addr 0xF4]. 7 -- 6 DPLL_ERR 5 RX3_ERR 4 RX2_ERR 3 RX1_ERR 2 TX3_ERR 1 TX2_ERR 0 TX1_ERR TX1_ERR-TX3_ERR Transmit Channel Error--Reported coincident with the TX_ERR interrupt to indicate which of the three HDSL transmit channels caused the TX_ERR. The MPU reads the respective channel's transmit status [STATUS_3; addr 0x07] to determine the specific error. 0 = No error 1 = Transmit error RX1_ERR-RX3_ERR Receive Channel Error--Reported coincident with the RX_ERR interrupt to indicate which of the three HDSL receive channels caused the RX_ERR. The MPU reads the respective channel's receive status [STATUS_1-STATUS_2; addr 0x05-0x06] to determine the specific error. 0 = No error 1 = Receive error DPLL_ERR DPLL Phase Detector Error--Reported coincident with the RX_ERR interrupt to indicate when the DPLL phase detector output reached the maximum or minimum phase error limit. 0 = No error 1 = DPLL error 4-64 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.15 PRA Transmit Read 4.15 PRA Transmit Read Table 4-12. PRA Transmit Read Registers Address 0x40 0x41 0x42 0x43 0x45 0x46 0x47 Register Label TX_PRA_CTRL0 TX_PRA_CTRL1 TX_PRA_MON1 TX_PRA_E_CNT TX_PRA_CODE TX_PRA_MON0 TX_PRA_MON2 Bits 8 7 8 8 6 6 4 Name/Description PRA Transmit Control Register 0 PRA Transmit Control Register 1 PRA Transmit Monitor Register 1 PRA Transmit E-Bits Register 0 PRA Transmit In-Band Code PRA Transmit Monitor Register 0 PRA Transmit Monitor Register 2 0x40--PRA Transmit Control Register 0 (TX_PRA_CTRL0) 7 E_MODE[1:0] 6 5 SA8_MODE 4 SA7_MODE 3 SA6_MODE[1:0] 2 1 SA5_MODE 0 SA4_MODE SA4_MODE Controls the behavior of Sa4 bits transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 1 SA5_MODE Controls the behavior of Sa5 bits transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 0 SA6_MODE Controls the behavior of Sa6 bits transmitted towards the HDSL link, as follows: Code 00 01 10 11 Sa6 Bits Transparent From bits buffer 0 Automatic Illegal The Automatic mode operates based on the result of the receiver (PCM to HDSL) CRC check and E-bits, as follows: Received E-bits 0 (Error) 0 (Error) 1 (No Error) 1 (No Error) NOTE: Receive CRC Check Error No Error Error No Error Sa6 0011 0001 0010 From bits buffer 0 (sec0) MSB of Sa6 is transmitted first (i.e., in frames 1 and 9). N8953BDSB Conexant 4-65 4.0 Registers 4.15 PRA Transmit Read SA7_MODE RS8953B/8953SPB HDSL Channel Unit Controls the behavior of Sa7 bits, transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 1 SA8_MODE Controls the behavior of Sa8 bits transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 1 E_MODE Controls the behavior of the E-bits transmitted towards the HDSL link, as follows: Code 00 01 10 11 E-bits Transparent From bits buffer 0 Automatic Illegal The Automatic mode operates in conjunction with the receiver CRC4 check result (reported also in RX_PRA_MON0), as follows: Receiver CRC Check Error OK NOTE: E-bits Forced to 0 1 The value of this register takes effect starting with the next PCM multiframe following the write access cycle completion. 0x41--PRA Transmit Control Register 1 (TX_PRA_CTRL1) 7 -- 6 RESET_E_CNT 5 AIS 4 A_MODE 3 2 1 SYNCHR_EN 0 PRA_EN CRC4_MODE[1:0] PRA_EN Used to enable or globally disable the receive PRA circuitry, as follows: 0 = Disable ALL RX PRA functionality 1 = Enable ALL RX PRA functionality SYNCHR_EN Used to enable or disable the PCM multiframe synchronization state machine, as follows: 0 = Enable--Use TMSYNC input pin as a qualifier of the frame, and force the synchronization state machine to HUNT mode 1 = Disable--Use TMSYNC input as a qualifier of multiframe CRC4_MODE CRC4_MODE controls the behavior of the CRC bits transmitted towards the HDSL link, as follows: Code 00 01 10 11 CRC4 Bits Transparent All 1 Re-calculated Illegal A_MODE Controls the behavior of A-bits transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 0 4-66 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit AIS 4.0 Registers 4.15 PRA Transmit Read Enables to override all 32 slots of an PCM frame except Slot 0, transmitted towards the HDSL link, with a constant pattern: 0 = Disable (Normal) 1 = 0xFF AIS must be activated with reset_e_cnt = 1 NOTE: AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern generation, use the existing feature of the channel unit. RST_E_CNT Clears the TX_E counter, as follows: 0 = Counter enabled 1 = Clear the E-transmit counter NOTE: The value of this register takes effect starting with the next PCM multiframe following the write access cycle completion. 0x42--PRA Transmit Monitor Register 1 (TX _PRA_MON1) 7 Sa6_4 6 Sa6_3 5 Sa6_2 4 Sa6_1 3 Sa5 2 A 1 E2 0 E1 This register is updated once every PCM multiframe. The bits in this register correspond to the bits in the transmitted PCM multiframe stream, in the PCM to HDSL direction. Sa6 _1, _2, _3, _4 Sa6 _1, _2, _3, _4 is updated only if the same Sa6 pattern is detected in the second submultiframe and synchr_en = 0. Sa5 is only updated if all 8 corresponding bits of the multiframe were detected as identical. A-bit is only updated if all 8 corresponding bits of the multiframe were detected as identical. E1is the E-bit detected in Frame 13. E2 is the E-bit detected in Frame 15. Sa5 A E1 E2 0x43--PRA Transmit E-Bits Counter (TX _PRA_E_CNT) 7 6 5 4 3 2 1 0 TX_PRA_E_CNT[7:0] The register is update twice in an PCM multiframe. It increments each time one of the E-bits is detected active 0. The counter wraps around at 255. It is cleared or enabled by RESET_E_CNT of TX_PRA_CTRL1 register. 0x45--PRA Transmit In-Band Code (TX_PRA_CODE) 7 Sa6_4 6 Sa6_3 5 Sa6_2 4 Sa6_1 3 -- 2 -- 1 Sa5 0 A N8953BDSB Conexant 4-67 4.0 Registers 4.15 PRA Transmit Read RS8953B/8953SPB HDSL Channel Unit This register is updated once every PCM multiframe. The bits in this register correspond to the bits in the transmitted PCM multiframe stream, in the PCM to HDSL direction. Sa6 _1, _2, _3, _4 Sa6 _1, _2, _3, _4 is updated only if detected identical in the last 8 submultiframes, given that the respective field was not masked in TX_BITS_BUF1. Sa5 is only updated only if detected identical in the last 8 submultiframes, given that the respective field was not masked in TX_BITS_BUF1. A-bit is only updated only if detected identical in the last 8 submultiframes, given that the respective field was not masked in TX_BITS_BUF1. Sa5 A 0x46--PRA Transmit Monitor Register 0 (TX_PRA_MON0) 7 SYNCH_STATE 6 Sa8 5 Sa7 4 Sa4 3 -- 2 -- 1 CRC error2 0 CRC error1 CRC error 1 CRC error 2 Sa4, Sa7, and Sa8 SYNCH_STATE Represents the CRC check result in submultiframe 1. Represents the CRC check result in submultiframe 2. Updated with a value that represents the majority over the eight off-frames. Represents the status of the multiframe synchronization machine. 0 = Not synchronized 1 = Synchronized If SYNCH_STATE is 1, the relative frame with which synchronization was achieved in TX_PRA_MON2 is readable. 0x47--PRA Transmit Monitor Register 2 (TX_PRA_MON2) 7 -- 6 -- 5 -- 4 -- 3 2 1 0 TX_PRA_MON2[3:0] The 4 bits of this register represent the original number of the relative frame with which synchronization was achieved. This is relevant only if bit SYNCH_STATE of TX_PRA_MON0 reads 1. 4-68 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.16 PRA Transmit Write 4.16 PRA Transmit Write Table 4-13. PRA Transmit Write Registers Address 0x70 0x71 0x72 0x73 0x74 Register Label TX_PRA_CTRL0 TX_PRA_CTRL1 TX_BITS_BUFF1 TX_PRA_TMSYNC_OFFSET TX_BITS_BUFFO Bits 8 7 6 8 8 Name/Description PRA Transmit Control Register 0 PRA Transmit Control Register 1 PRA Transmit Bits Buffer 1 PRA Transmit TMSYNC Offset Register PRA Transmit Bits Buffer 0 0x70--PRA Transmit Control Register 0 (TX_PRA_CTRL0) 7 E_MODE[1:0] 6 5 SA8_MODE 4 SA7_MODE 3 SA6_MODE[1:0] 2 1 SA5_MODE 0 SA4_MODE SA4_MODE Controls the behavior of Sa4 bits transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 1 SA5_MODE Controls the behavior of Sa5 bits transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 0 SA6_MODE Controls the behavior of Sa6 bits transmitted towards the HDSL link, as follows: Code 00 01 10 11 Sa6 Bits Transparent From bits buffer 0 Automatic Illegal The Automatic mode operates based on the result of the receiver (HDSL to PCM) CRC check and E-bits, as follows: Received E-bits 0 (Error) 0 (Error) 1 (No Error) 1 (No Error) NOTE: Receive CRC Checks Error No Error Error No Error Sa6 0011 0001 0010 From bits buffer 0 (sec 0) MSB of Sa6 is transmitted first (i.e., in frames 1 and 9). SA7_MODE Controls the behavior of Sa7 bits transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 1 N8953BDSB Conexant 4-69 4.0 Registers 4.16 PRA Transmit Write SA8_MODE RS8953B/8953SPB HDSL Channel Unit Controls the behavior of Sa8 bits, transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 1 E_MODE Controls the behavior of the E-bits transmitted towards the HDSL link, as follows: Code 00 01 10 11 E-bits Transparent From bits buffer 0 Automatic Illegal The Automatic mode operates in conjunction with the receiver CRC4 check result (reported also in RX_PRA_MON0), as follows: Receiver CRC Check Error OK NOTE: E-bits Forced to 0 1 The value of this register takes effect starting with the next PCM multiframe following the write access cycle completion. 0x71--PRA Transmit Control Register 1 (TX_PRA_CTRL1) 7 -- 6 RESET_E_CNT 5 AIS 4 A_MODE 3 2 1 SYNCHR_EN 0 PRA_EN CRC4_MODE[1:0] PRA_EN Enable or globally disable the receive PRA circuitry, as follows: 0 = Disable ALL RX PRA functionality 1 = Enable ALL RX PRA functionality SYNCHR_EN Enable or disable the PCM multiframe synchronization state machine, as follows: 0 = Enable. Use TMSYNC input pin as a qualifier of the frame and force synchronization state machine to HUNT mode. 1 = Disable. Use TMSYNC input as a qualifier of multiframe. CRC4_MODE Controls the behavior of the CRC bits, transmitted towards the HDSL link, as follows: Code 00 01 10 11 CRC4 Bits Transparent All `1's Re-calculated Illegal A_MODE Controls the behavior of A-bits, transmitted towards the HDSL link, as follows: 0 = Transparent 1 = From bits buffer 0 4-70 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit AIS 4.0 Registers 4.16 PRA Transmit Write Enables to override all 32 slots of an PCM frame except slot 0 transmitted towards the HDSL link, with a constant pattern: 0 = Disable (Normal) 1 = 0xFF NOTE: AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern generation, use the existing feature of the channel unit. RST_E_CNT Clears the TX_E counter 0 = Counter enabled 1 = Clear the E transmit counter NOTE: The value of this register takes effect starting with the next PCM multiframe following the write access cycle completion. 0x72--PRA Transmit Bits Buffer 1 (TX_BITS_BUFF1) 7 -- 6 SA6_MASK 5 SA5_MASK 4 A_MASK 3 -- 2 Sa8 1 Sa7 0 Sa4 The value of this register is only relevant if the corresponding MODE bit of TX_PRA_CTRL0 is set. A new written value takes effect starting with the next PCM multiframe, following the register write access cycle completion. An in-band code is reported as detected when the pattern in the Sa6, Sa5, AND A fields remain constant for 8 consecutive multiframes. Sa4 Sa7 Sa8 A_MASK The new value to be inserted into the Sa4 location of the data stream, in the PCM to HDSL direction. The new value to be inserted into the Sa7 location of the data stream, in the PCM to HDSL direction. The new value to be inserted into the Sa8 location of the data stream, in the PCM to HDSL direction. Determines whether the pattern in the A-bit field must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. Determines whether the pattern in the SA5 field must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. Determines whether the pattern in the SA6 field must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. SA5_MASK SA6_MASK 0x73--PRA Transmit TMSYNC offset Register (TX_PRA_TMSYNC_OFFSET) 7 6 5 4 3 2 1 0 TX_PRA_TMSYNC_OFFSET[7:0] The value of this register is used to enable the accommodation of the RS8953B to any TMSYNC signal shape. When programmed to 0x00, the PRA circuitry assumes that the positive edge of the TMSYNC input signal coincides with the first bit of an PCM framer. N8953BDSB Conexant 4-71 4.0 Registers 4.16 PRA Transmit Write RS8953B/8953SPB HDSL Channel Unit When this assumption is not valid, this register may be used to internally reposition the TMSYNC to coincide with Bit 0. 0x74--PRA Transmit Bits Buffer 0 (TX_BITS_BUFF0) 7 Sa6_4 6 Sa6_3 5 Sa6_2 4 Sa6_1 3 Sa5 2 A 1 E2 0 E1 The value of this register is only relevant if the corresponding MODE bit of TX_PRA_CTRL0 is set. A new written value takes effect starting with the next PCM multiframe following the register write access cycle completion. Each bit of this register is used in the odd frames of the PCM multiframe. E1 The new value to be inserted into the E1 location of the data stream, in the PCM to HDSL direction. E1 is used in Frame 13. The new value to be inserted into the E2 location of the data stream, in the PCM to HDSL direction. E2 is used in Frame 15. The new value to be inserted into the A-bit location of the data stream, in the PCM to HDSL direction. A-bit is used in all odd frames. The new value to be inserted into the Sa5 location of the data stream, in the PCM to HDSL direction. Sa5 is used in all odd frames. The new value to be inserted into the Sa6 _1, _2, _3, _4 location of the data stream, in the PCM to HDSL direction. Sa6 _1 is used in Frames 1 and 9. Sa6 _2 is used in Frames 3 and 11. Sa6 _3 is used in Frames 5 and 13. Sa6 _4 is used in Frames 7 and 15. E2 A Sa5 Sa6 _1, _2, _3, _4 4-72 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.17 PRA Receive Read 4.17 PRA Receive Read Table 4-14. PRA Receive Read Registers Address 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 Register Label RX_PRA_CTRL0 RX_PRA_CTRL1 RX_BITS_BUFF1 RX_PRA_E_CNT RX_PRA_CRC_CNT RX_PRA_CODE RX_PRA_MON0 RX_PRA_MON2 Bits 7 8 8 8 8 6 6 4 Name/Description PRA Receive Read Register 0 PRA Receive Control Register 1 PRA Receive Bits Buffer 1 PRA Receive E Bit Counter PRA Receive CRC4 Error Counter PRA Receive In-Band Code PRA Receive Monitor Register 0 PRA Receive Monitor Register 2 0x80--PRA Receive Control Register 0 (RX_PRA_CTRL0) 7 E_MODE[1:0] 6 5 SA8_MODE 4 SA7_MODE 3 -- 2 SA6_MODE 1 SA5_MODE 0 SA4_MODE SA4_MODE Controls the behavior of Sa4 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 1 SA5_MODE Controls the behavior of Sa5 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 1 SA6_MODE Controls the behavior of Sa6 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 0 SA7_MODE Controls the behavior of Sa7 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 1 SA8_MODE Controls the behavior of Sa8 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 1 N8953BDSB Conexant 4-73 4.0 Registers 4.17 PRA Receive Read E_MODE RS8953B/8953SPB HDSL Channel Unit Controls the behavior of the E-bits transmitted towards the HDSL link, as follows: Code 00 01 10 11 E-bits Transparent From Bits Buffer 0 Automatic Illegal The Automatic mode works in conjunction with the transmitter CRC4 check result (reported also in TX_PRA_MON0), as follows: Receiver CRC Check Error OK NOTE: E-bits Forced to: 0 1 The value of this register takes effect starting with the next PCM multiframe following the write access cycle completion. 0x81--PRA Receive Control Register 1 (RX_PRA_CTRL1) 7 RESET_CRC_CNT 6 RESET_E_CNT 5 AIS 4 A_MODE 3 2 1 SYNCHR_EN 0 PRA_EN CRC4_MODE[1:0] PRA_EN Used to enable or globally disable the transmit PRA circuitry, as follows: 0 = Disable ALL TX PRA functionality 1 = Enable ALL TX PRA functionality SYNCHR_EN Used to enable or disable the PCM multiframe synchronization state machine, as follows: 0 = Enable synchronization and force HUNT mode. Take RMSYNC as indicator of frame. 1 = Disable synchronization. Take RMSYNC as multiframe indicator. CRC4_MODE Controls the behavior of the CRC bits, transmitted towards the PCM link, as follows: Code 00 01 10 11 E-bits Transparent All 1 Re-calculated Illegal A_MODE Controls the behavior of A-bits, transmitted towards the PCM link, as follows: 0 = Transparent 1 = From bits buffer 0 AIS Enables to override all 32 slots of an PCM frame except slot 0, transmitted towards the PCM link with a constant pattern: 0 = Disable (Normal) 1 = 0xFF NOTE: AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern generation, use the existing feature of the channel unit. 4-74 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit RST_E_CNT 4.0 Registers 4.17 PRA Receive Read Clears the RX_E counter, as follows: 0 = Counter enabled 1 = Clear the E-receive counter RST_CRC_CNT Clears the RX_CRC counter, as follows: 0 = Counter enabled 1 = Clear the E-receive counter NOTE: The value of this register takes effect starting with the next PCM multiframe following the write access cycle completion. 0x82--PRA Receive Monitor Register 1 (RX _PRA_MON1) 7 Sa6_4 6 Sa6_3 5 Sa6_2 4 Sa6_1 3 Sa5 2 A 1 E2 0 E1 The register is updated once every PCM multiframe. SA5 and A-bit are updated with a value that represents the majority of identical corresponding bits (5 or more). E1 The value monitored from the E1 location of the data stream, in the HDSL to PCM direction. E1 is the bit detected in Frame 13. The value monitored from the E2 location of the data stream, in the HDSL to PCM direction. E2 is the bit detected in Frame 15. The value monitored from the A-bit location of the data stream, in the HDSL to PCM direction. The value monitored from the Sa5 location of the data stream, in the HDSL to PCM direction. The value monitored from the Sa6 _1, _2, _3, _4 location of the data stream, in the HDSL to PCM direction. Sa6 _1, _2, _3, _4 is updated only if the same Sa6 pattern is detected in the second submultiframe and synchr_en = 0. E2 A Sa5 Sa6 _1, _2, _3, _4 0x83--PRA Receive E bits Counter (RX_PRA_E_CNT) 7 6 5 4 3 2 1 0 RX_PRA_E_CNT[7:0] The register is updated twice in a PCM multiframe. It increments each time one of the E-bits is detected active 0. The counter wraps around at 255. It is cleared/enabled by RESET_E_CNT of RX_PRA_CTRL1 register. 0x84--PRA Receive CRC4 Errors Counter (RX_PRA_CRC_CNT) 7 6 5 4 3 2 1 0 RX_PRA_CRC_CNT[7:0] N8953BDSB Conexant 4-75 4.0 Registers 4.17 PRA Receive Read RS8953B/8953SPB HDSL Channel Unit The register is updated twice each PCM multiframe. It increments each time a mismatch between the reported and calculated CRC4 is detected. The counter wraps around at 255. It is cleared/enabled by RESET_CRC_CNT of RX_PRA_CTRL1 register. 0x85--PRA Receive In-Band Code (RX_PRA_CODE) 7 Sa6_4 6 Sa6_3 5 Sa6_2 4 Sa6_1 3 -- 2 -- 1 Sa5 0 A This register is updated with a value, only if it was detected identical in the last 8 submultiframes, given the respective field was not masked in RX_BITS_BUF1. A Sa5 Sa6 _1, _2, _3, _4 The value from the A-bit location of the data stream, in the HDSL to PCM direction. The value from the Sa5 location of the data stream, in the HDSL to PCM direction. The value from the Sa6 _1, _2, _3, _4 location of the data stream, in the HDSL to PCM direction. 0x86--PRA Receive Monitor Register 0 (RX_PRA_MON0) 7 SYNCH_STATE 6 Sa8 5 Sa7 4 Sa4 3 -- 2 -- 1 CRC error2 0 CRC error1 CRC error1 CRC error2 Sa4, Sa7, and Sa8 SYNCH_STATE Represents the CRC check result in submultiframe 1. Represents the CRC check result in submultiframe 2. Updated with the value that represents the majority of identical respective bits (5 or more). Represents the status of the multiframe synchronization machine, as follows: 0 = Not synchronized 1 = Synchronized If SYNCH_STATE reads 1, the offset frame with which synchronization was achieved in RX_MON2 is readable. 0x87--PRA Receive Monitor Register 2 (RX_PRA_MON2) 7 -- 6 -- 5 -- 4 -- 3 2 1 0 RX_PRA_MON2[3:0] The 4 bits of this register represent the original number of the relative frame with which synchronization was achieved. This is relevant only if bit SYNCH_STATE of RX_PRA_MON0 reads 1. 4-76 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 4.0 Registers 4.18 PRA Receive Write 4.18 PRA Receive Write Table 4-15. PRA Receive Write Registers Address 0xB0 0xB1 0xB2 0xB4 Register Label RX_PRA_CTRL0 RX_PRA_CTRL1 RX_BITS_BUFF1 RX_PRA_BUFF0 Bits 7 8 6 8 Name/Description PRA Receive Read Register 0 PRA Receive Control Register 1 PRA Receive Bits Buffer 1 PRA Receive Bit Counter 0xB0--PRA Receive Control Register 0 (RX_PRA_CTRL0) 7 E_MODE[1:0] 6 5 SA8_MODE 4 SA7_MODE 3 -- 2 SA6_MODE 1 SA5_MODE 0 SA4_MODE SA4_MODE Controls the behavior of Sa4 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 1 SA5_MODE Controls the behavior of Sa5 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 0 SA6_MODE Controls the behavior of Sa6 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 0 SA7_MODE Controls the behavior of Sa7 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 1 SA8_MODE Controls the behavior of Sa8 bits transmitted towards PCM, as follows: 0 = Transparent 1 = From bits buffer 1 E_MODE Controls the behavior of the E-bits transmitted towards the HDSL link, as follows: Code 00 01 10 11 E-bits Transparent From bits buffer 0 Automatic Illegal N8953BDSB Conexant 4-77 4.0 Registers 4.18 PRA Receive Write RS8953B/8953SPB HDSL Channel Unit The Automatic mode operates in conjunction with the transmitter CRC4 check result (reported also in TX_PRA_MON0), as follows: Receiver CRC Check Error OK NOTE: E-bits Forced to: 0 1 The value of this register takes effect starting with the next PCM multiframe following the write access cycle completion. The unused bit (bit 3) should be set to a value of 0. 0xB1--PRA Receive Control Register 1 (RX_PRA_CTRL1) 7 RESET_CRC_CNT 6 RESET_E_CNT 5 AIS 4 A_MODE 3 2 1 SYNCHR_EN 0 PRA_EN CRC4_MODE[1:0] PRA_EN Used to enable or globally disable the transmit PRA circuitry, as follows: 0 = Disable ALL TX PRA functionality 1 = Enable ALL TX PRA functionality SYNCHR_EN Used to enable or disable the PCM multiframe synchronization state machine, as follows: 0 = Enable synchronization and force HUNT mode. Take RMSYNC as indicator of frame. 1 = Disable synchronization. Take RMSYNC as multiframe indicator. CRC4_MODE Controls the behavior of the CRC bits transmitted towards the PCM link, as follows: Code 00 01 10 11 CRC4 Bits Transparent All 1 Re-calculated Illegal A_MODE Controls the behavior of A-bits transmitted towards the PCM link, as follows: 0 = Transparent 1 = From bits buffer 0 AIS Enables to override all 32 slots of an PCM frame except slot 0, transmitted towards the PCM link with a constant pattern: 0 = Disable (Normal) 1 = 0xFF AIS must be activated with reset_e_cnt = 1. NOTE: AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern generation, use the existing feature of the channel unit. RST_E_CNT Clears the RX_E counter, as follows: 0 = Counter enabled 1 = Clear the E-receive counter 4-78 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit RST_CRC_CNT 4.0 Registers 4.18 PRA Receive Write Clears the RX_CRC counter, as follows: 0 = Counter enabled 1 = Clear the E-receive counter NOTE: The value of this register takes effect starting with the next PCM multiframe, following the write access cycle completion. 0xB2--PRA Receive Bits Buffer 1 (RX_BITS_BUFF1) 7 -- 6 Sa6_MASK 5 Sa6_MASK 4 Sa6_MASK 3 -- 2 Sa8 1 Sa7 0 Sa4 The value of this register is only relevant if its corresponding MODE bit of RX_PRA_CTRL0 is set. A new written value takes effect starting with the next PCM multiframe following the register write access cycle completion. An in-band code is reported as detected when the pattern in the Sa6, Sa5, AND A fields remain constant for 8 consecutive multiframes. Sa4 Sa7 Sa8 A_MASK The new value to be inserted into the Sa4 location of the data stream, in the HDSL to PCM direction. The new value to be inserted into the Sa7 location of the data stream, in the HDSL to PCM direction. The new value to be inserted into the Sa8 location of the data stream, in the HDSL to PCM direction. Determines if the pattern in the A-bit field must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. Determines if the pattern in the SA5 field must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. Determines if the pattern in the SA6 field must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. SA5_MASK SA6_MASK 0xB4--PRA Receive Bits Buffer 0 (RX_BITS_BUFF0) 7 Sa6_4 6 Sa6_3 5 Sa6_2 4 Sa6_1 3 Sa5 2 A 1 E2 0 E1 The value of this register is only relevant if the corresponding MODE bit of RX_PRA_CTRL0 is set. A new written value takes effect starting with the next PCM multiframe, following the register write access cycle completion. Each bit of this register is used in the odd frames of the PCM multiframe. E1 The new value to be inserted into the E1 location of the data stream, in the HDSL to PCM direction. E1 is used in Frame 13. The new value to be inserted into the E2 location of the data stream, in the HDSL to PCM direction. E2 is used in Frame 15. The new value to be inserted into the A-bit location of the data stream, in the HDSL to PCM direction. A-bit is used in all odd frames. E2 A N8953BDSB Conexant 4-79 4.0 Registers 4.18 PRA Receive Write Sa5 Sa6 _1, _2, _3, _4 RS8953B/8953SPB HDSL Channel Unit The new value to be inserted into the Sa5 location of the data stream, in the HDSL to PCM direction. Sa5 is used in all odd frames. The new value to be inserted into the Sa6 _1, _2, _3, _4 location of the data stream, in the HDSL to PCM direction. Sa6 _1 is used in Frames 1 and 9. Sa6 _2 is used in Frames 3 and 11. Sa6 _3 is used in Frames 5 and 13. Sa6 _4 is used in Frames 7 and 15. 4-80 Conexant N8953BDSB 5 5.0 Applications The following chapter shows typical interconnections of the RS8953B HDSL channel unit: * * * * Conexant HDSL Transceiver Bt8370 E1/T1 Primary Rate Framer Motorola 68302 16-bit Processor Intel 8051 8-bit Processor N8953BDSB Conexant 5-1 5.0 Applications 5.1 Interfacing to a Conexant HDSL Transceiver RS8953B/8953SPB HDSL Channel Unit 5.1 Interfacing to a Conexant HDSL Transceiver Figure 5-1 illustrates a typical interconnection between the RS8953B HDSL channel unit and a Conexant HDSL transceiver. Figure 5-1. RS8953B HDSL Channel Unit to Conexant HDSL Transceiver Interconnection TQ[0] TDAT1 QCLK1 RDAT1 BCLK1 TQ[1] QCLK RQ[1] RQ[0] HDSL Transceiver RS8953B TQ[0] TDAT2 QCLK2 RDAT2 BCLK2 TQ[1] QCLK RQ[1] RQ[0] HDSL Transceiver TQ[0] TDAT3 QCLK3 RDAT3 BCLK3 TQ[1] QCLK RQ[1] RQ[0] HDSL Transceiver Optional NOTE(S): Loop Quat Clock (QCLKn) when low, qualifies the sign bit on the Loop Receive Data (RDATn). 5-2 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 5.0 Applications 5.2 Interfacing to the Bt8370 E1/T1 Framer 5.2 Interfacing to the Bt8370 E1/T1 Framer Figure 5-2 illustrates a typical interconnection between the RS8953B HDSL channel unit and the Bt8370 E1/T1 framer. Figure 5-2. RS8953B HDSL Channel Unit to Bt8360 DS1 Framer Interconnection RSBCKI/RCKO RPCMO RMSYNC Bt8370 TPCMI TSBCKI/TCKI TMSYNC RSER RCLK RMSYNC TCLK TSER TMSYNC RS8953B N8953BDSB Conexant 5-3 5.0 Applications 5.3 Interfacing to the 68302 Processor RS8953B/8953SPB HDSL Channel Unit 5.3 Interfacing to the 68302 Processor Figure 5-3 illustrates a typical interconnection between the RS8953B HDSL channel unit and the 68302 processor. Figure 5-3. RS8953B to 68302 Processor Interconnection VCC MPUSEL A[15] MC68302 AS DS R/W CS* ALE RD* WR* RS8953B A[7:0] D[7:0] Mux Logic AD[7:0] IRQ6 INTR* 5-4 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 5.0 Applications 5.4 Interfacing to the 8051 Controller 5.4 Interfacing to the 8051 Controller Figure 5-4 illustrates a typical interconnection between the RS8953B HDSL channel unit and the 8051 controller. Figure 5-4. RS8953B HDSL Channel Unit to 8051 Controller Interconnection MPUSEL 8051 AD[15] ALE WR RD AD[7:0] INT0 CS* ALE WR* RD* AD[7:0] INTR* RS8953B N8953BDSB Conexant 5-5 5.0 Applications 5.5 References RS8953B/8953SPB HDSL Channel Unit 5.5 References Applicable specifications: * Bellcore TA-NWT-001210 * Bellcore FA-NWT-001211 * ETSI RTR/TM-03036 * CCITT Recommendation G.704 * Bellcore TR-NWT-000499 5-6 Conexant N8953BDSB 6 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings Table 6-1. Absolute Maximum Ratings Symbol VCC VI TST TVSOL Supply Voltage Voltage on Any Signal Pin Storage Temperature Vapor Phase Soldering Temperature (1 minute) Thermal Resistance (68 PLCC), Still Air Parameter Minimum -0.3 -1.0 -40 Maximum 7 5.3 125 220 39.8 Units V V C C C/ JA W NOTE(S): Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6.1.1 Recommended Operating Conditions Table 6-2. Recommended Operating Conditions Symbol VCC TAMB VIH VIL Supply Voltage Ambient Operating Temperature High-Level Input Voltage Low-Level Input Voltage Parameter Minimum 3.0 -40 2.0 -0.3 Maximum 3.6 85 VEXT +.25 0.8 Units V C V V N8953BDSB Conexant 6-1 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings RS8953B/8953SPB HDSL Channel Unit 6.1.2 Electrical Characteristics Table 6-3. Electrical Characteristics Symbol ICC Parameter Supply Current PCM = 4.096 Mbps HDSL = 2.320 Mbps Supply Current 1T1 Supply Current 2T1 Supply Current 1E1 Supply Current 2E1 Supply Current 3E1 Minimum Maximum 21.1 Units mA 11.6 9.8 13.8 10.9 10.7 2.4 200 0.4 2 4 4 40 -10 -10 500 10 10 2.5 70 85 37 160 mA mA mA mA mA V A V mA mA A A A pF pF pF mA VOH IOH VOL IOL IOD IPR II IOZ CIN CLD CZ IOSC High-Level Output Voltage High-Level Output Current Source Low-Level Output Voltage Low-Level Output Current Sink Open Drain Output Current Sink Resistive Pullup Current Input Leakage Current Three-State Leakage Current Input Capacitance Output Capacitive Loading High-Impedance Output Capacitance Short Circuit Output Current 6-2 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings 6.1.3 Timing Requirements Figure 6-1. Input Clock Timing Input Clock Tf Th Tp Tl Tr Table 6-4. Clock Timing Requirements Symbol 1/ Tp Parameter Mclk Frequency (Pll_dis = 0; Pll_mul = 16) Mclk Frequency (Pll_dis = 0; Pll_mul = 8) Mclk Frequency (Pll_dis = 1) Tclk, Exclk Frequency Bclkn Frequency Tck Frequency Minimum 3.75 7.5 60 0.128 0.144 0 0.4 x TP 0.4 x TP Maximum 5.0 10 80 4.096 2.320 25 0.6 x TP 0.6 x TP 20 20 Units MHz MHz MHz MHz MHz MHz ns ns ns ns Th Tl Tr Tf Clock Width High Clock Width Low Clock Rise Time Clock Fall Time Figure 6-2. Input Setup and Hold Timing Input Clock Ts Thld Falling Edge Input Sample Ts Thld Rising Edge Input Sample N8953BDSB Conexant 6-3 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings RS8953B/8953SPB HDSL Channel Unit Table 6-5. Data Timing Requirements Symbol Ts Thld Input Setup Time Input Hold Time Parameter Minimum 35 10 Maximum Units ns ns Table 6-6. Input Clock Edge Selection Clock Edge Inputs HDSL Channel Inputs BCLK1 BCLK2 BCLK3 Falling Falling Falling QCLK1, RDAT1, TAUX1 QCLK2, RDAT2, TAUX2 QCLK3, RDAT3, TAUX3 PCM Channel Inputs TCLK TCLK RCLK RCLK EXCLK EXCLK EXCLK EXCLK Falling Rising Falling Rising Falling Rising Falling Rising TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC Test Access Inputs TCK Rising TMS, TDI -- 00 01 1x 1x 1x 1x 1x 1x -- -- 00 00 01 01 10 10 -- -- 0 1 0 1 0 1 -- TCLK_SEL (CMD_2) RCLK_SEL (CMD_2) RCLK_INV (CMD_7) 6-4 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings 6.1.4 Switching Characteristics Figure 6-3. Output Clock and Data Timing Tp Th Output Clock Tf Thld Falling Edge Outputs Tdly Thld Rising Edge Outputs Tdly Tr Tl Table 6-7. Clock and Data Switching Characteristics Symbol 1/Tp Parameter SCLK Frequency RCLK Frequency Minimum 15 0.064 TP-20 TP-20 Maximum 20 4.1 TP+20 TP+20 15 15 Units MHz MHz ns ns ns ns ns Th Tl Tr Tf Thld Tdly Clock Width High Clock Width Low Clock Rise Time Clock Fall Time Output Data Hold Output Data Delay 0 25 ns N8953BDSB Conexant 6-5 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings RS8953B/8953SPB HDSL Channel Unit Table 6-8. Output Clock Edge Selection Clock Edge Outputs HDSL Channel Outputs BCLK1 BCLK2 BCLK3 Rising Rising Rising TDAT1, TLOAD1, RAUX1, ROH1 TDAT2, TLOAD2, RAUX2, ROH2 TDAT3, TLOAD3, RAUX3, ROH3 PCM Transmit Channel Outputs TCLK TCLK RCLK RCLK EXCLK EXCLK Rising Falling Rising Falling Rising Falling MSYNC, INSERT MSYNC, INSERT MSYNC, INSERT MSYNC, INSERT MSYNC, INSERT MSYNC, INSERT PCM Receive Channel Outputs RCLK RCLK EXCLK EXCLK TCLK TCLK Rising Falling Rising Falling Rising Falling RSER, RMSYNC, DROP RSER, RMSYNC, DROP RSER, RMSYNC, DROP RSER, RMSYNC, DROP RSER, RMSYNC, DROP RSER, RMSYNC, DROP Test Access Outputs TCK Falling TDO -- -- -- -- -- 00 01 00 00 01 10 11 11 0 1 0 0 0 0 00 01 1x 1x 1x 1x -- -- 00 00 01 10 -- -- 0 1 0 0 -- TCLK_SEL (CMD_2) RCLK_SEL (CMD_2) RCLK_INV (CMD_7) 6-6 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings 6.1.5 MPU Interface Timing Motorola- (MPUSEL = 1) and Intel- (MPUSEL = 0) style microprocessor bus timing, as follows: Table 6-9. MPU Interface Timing Requirements Symbol 1 2 3 5 6 7 8 9 10 ALE Pulse-Width High Address Input Setup to ALE Falling Address Input Hold after ALE Low Data Input Setup to End of Write Pulse Data Input Hold After Write Pulse WR* Setup to Start of Read or Write Pulse WR* Hold after Read or Write Pulse ALE Hold after Read or Write Pulse Write Pulse-Width: WR*, RD*, and CS* Low (MPUSEL = 1) RD* = 1, WR*, and CS* Low (MPUSEL = 0) Read Pulse Width (WR* = 1, RD* and CS* Low) Read Pulse Width (WR* = 1, RD* and CS* Low) Address = 0x3C only. Parameter Minimum 20 10 7 10 8 10 10 8 12 x ------------f GCLK 26 1 2 x ------------f GCLK Maximum Units ns ns ns ns ns ns ns ns ns 11 ns ns Table 6-10. MPU Interface Switching Characteristics Symbol 12 13 14 15 16 17 Parameter Data Out Enable (Low Z) after Start of Read Pulse Data Out Valid After Start of Read Pulse (Access Time) Data Out Hold After End of Read Pulse Data Out Disable (High Z) after End of Read Pulse INTR* Hold After End of Write Pulse (when writing interrupt mask or clear registers) INTR* Delay from End of Write Pulse (when writing interrupt mask or enable registers) Minimum 2 Maximum Units ns 26 1 25 5 20 ns ns ns ns ns N8953BDSB Conexant 6-7 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings RS8953B/8953SPB HDSL Channel Unit Figure 6-4. MPU Write Timing, MPUSEL = 1 ALE 1 2 AD[7:0] 3 ADDRESS 5 CS* RD* (Data Strobe) 7 WR* (Write Enable) 17 16 INTR* 10 8 DATA INPUT 6 9 Figure 6-5. MPU Read Timing, MPUSEL = 1 ALE 1 2 AD[7:0] 3 ADDRESS DATA OUTPUT 14 12 13 RD* CS* 7 WR* (Read Enable) 11 8 15 9 6-8 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Figure 6-6. MPU Write Timing, MPUSEL = 0 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings ALE 1 2 AD[7:0] 3 ADDRESS 5 WR* CS* 10 17 16 INTR* 9 DATA INPUT 6 Figure 6-7. MPU Read Timing, MPUSEL = 0 ALE 1 2 AD[7:0] 3 ADDRESS DATA OUTPUT 14 12 13 RD* CS* 11 9 15 N8953BDSB Conexant 6-9 6.0 Electrical and Timing Specifications 6.2 Mechanical Specifications RS8953B/8953SPB HDSL Channel Unit 6.2 Mechanical Specifications Figure 6-8. 68-Pin PLCC Package Drawing 6-10 Conexant N8953BDSB RS8953B/8953SPB HDSL Channel Unit Figure 6-9. 80-Pin PQFP Mechanical Specification 6.0 Electrical and Timing Specifications 6.2 Mechanical Specifications S Y M B O L A A1 A2 D D1 D3 e E E1 E3 L b N8953BDSB Conexant 6-11 6.0 Electrical and Timing Specifications 6.2 Mechanical Specifications RS8953B/8953SPB HDSL Channel Unit 6-12 Conexant N8953BDSB 7 7.0 Acronyms, Abbreviations and Notation 7.1 Arithmetic Notation 7.1.1 Bit Numbering The Least Significant Bit (LSB) having the lowest number represents the lowest number within a bit. 7.1.2 Acronyms and Abbreviations AIS 2B1Q BER CMOS CO CRC DPLL EOC ESF FEBE JTAG HDSL HOH HRP HTU-C HTU-R LIU LOSD LOSW LSB LFSR MSB PQFP PLCC PRBS QUAT QRSS SF UIB N8953BDSB Alarm Indication Signal 2 Binary, 1 Quaternary Bit Error Rate Complementary Metal-Oxide Semiconductor Central Office HDSL Cyclic Redundancy Check Digital Phase Lock Loop HDSL Embedded Operations Channel Extended Superframe HDSL Far-End Block Error Joint Test Action Group High-Bit-Rate Digital Subscriber Line HDSL OverHead HDSL Repeater Present HDSL Terminal Unit at the Central Office HDSL Terminal Unit at the Remote Distribution Line Interface Unit Loss of Signal - DS1 HDSL Loss-of-Sync Word Least Significant Bit Linear Feedback Shift Register Most Significant Bit Plastic Quad Flat Pack Plastic Leaded Chip Carrier Pseudo-Random Binary Sequence Quaternary symbol Quasi-Random Sequence Signal Super Frame Unspecified Indicator Bit Conexant 7-1 7.0 Acronyms, Abbreviations and Notation 7.1 Arithmetic Notation RS8953B/8953SPB HDSL Channel Unit VCXO Voltage-Controlled Crystal Oscillator 7-2 Conexant N8953BDSB A Appendix A A.1 Differences Between Bt8953A and RS8953B Table A-1. Pin Definitions Pin Number 68 Pin PLCC 19 27 48 49 61 44 45 Bt8953A (5.0 V) Signal VCC VCC PLLVCC VCC (SCAN_MD) VCC LP1 LP2 RS8953B (3.3 V) Signal VCC VCC PLLVCC VCC (SCAN_MD) VCC VCC VEXT 80 Pin PQFP 13 23 48 49 63 43 45 Description 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V Multiplier PLL analog phase detector output Voltage level controls the VCO frequency of the multiplier PLL Description 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Input protection diodes bias N8953BDSB Conexant A-1 Appendix A A.1 Differences Between Bt8953A and RS8953B RS8953B/8953SPB HDSL Channel Unit Table A-2. Power Consumption Configuration Maximum 528 Kbps on single DSL / 2.048 Mbps on PCM 1040 Kbps on single DSL / 2.048 Mbps on PCM 1168 Kbps on single DSL / 2.048 Mbps on PCM 1T1 (1.552 Mbps on single DSL / 1.544 Mbps on PCM) 2T1 (784 Kbps on 2 DSL / 1.544 Mbps on PCM) 1E1 (2.320 Mbps on single DSL / 2.048 Mbps on PCM) 2E1 (1168 Kbps on 2 DSL / 2.048 Mbps on PCM) 3E1 (784 Kbps on 3 DSL / 2.048 Mbps on PCM) Bt8953A (5.0 V) 80 mA 30.5 mA 34.8 mA 36.2 mA -- -- -- 38.6 mA 41.3 mA RS8953B (3.3 V) 21.1 mA -- -- -- 11.6 mA 9.8 mA 13.8 mA 10.9 mA 10.7 mA A-2 Conexant N8953BDSB B Appendix B: Bt8953A/RS8953B Product Bulletin B.1 BCLK Phase Constraints In Repeater Mode; Non-Conformance Product Affected: Bt8953A and RS8953B While in repeater mode (REPEAT_EN = 1 for CH1 and CH2), a BCLK1 to BCLK2 phase difference of 180 degrees, +/- 5 nSec, will result in corrupted data transfer. All other phase relationships are acceptable. In a repeater mode application, to prevent a phase difference of 180 degrees between BCLK1 and BCLK2, the same clock is feed to both BCLK1 and BCLK2. To use the same clock for both HDSL transceivers, one HDSL transceiver needs to be slaved to the other HDSL transceiver. This is accomplished by setting the HDSL transceiver, which is configured as HTU-C, to "parallel slave mode." Then the parallel signals from the HDSL transceiver need to be externally converted to "serial, sign first mode" to interface to the Bt8953A/RS8953B. To configure the ZipWire transceiver to "parallel slave mode", address 0x06 of the ZipWire transceiver needs to be modified. Also to align the sign and magnitude data correctly, the tbclk_pol and rbclk_pol need to set properly. The tbclk_pol and rdbclk_pol are controlled by address 0x06 of the ZipWire transceiver. TQ[1,0] should be sampled on the falling edge of TBCLK. RQ[1,0] should be updated on the falling edge of RBCLK. N8953BDSB Conexant B-1 Appendix B : Bt8953A/RS8953B Product Bulletin RS8953B/8953SPB HDSL Channel B.1 BCLK Phase Constraints In Repeater Mode; Non-Conformance Product Affected: Bt8953A and RS8953B 1 0 CLK D Q HCLK BCLK QCLK TDAT RDAT MCLK BCLK1 QCLK1 TDAT1 RDAT1 BCLK2 QCLK2 TDAT2 RDAT2 1 0 0 1 CLK D Q MCLK TBCLK RBCLK TQ0 TQ1 RQ0 RQ1 HTU-R Bt8953A/RS8953B Zipwire Transceiver HTU-C Zipwire Transceiver B-2 Conexant N8953BDSB 0.0 Sales Offices Further Information literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com China Phone: (86 2) 6361 2515 Fax: (86 2) 6361 2516 Hong Kong Phone: (852) 2827 0181 Fax: (852) 2827 6488 India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 Korea Phone: (82 2) 565 2880 Fax: (82 2) 565 1440 World Headquarters Conexant Systems, Inc. 4311 Jamboree Road P. O. Box C Newport Beach, CA 92658-8902 Phone: (949) 483-4600 Fax: (949) 483-6375 U.S. Florida/South America Phone: (813) 799-8406 Fax: (813) 799-8306 U.S. Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Mid-Atlantic Phone: (215) 244-6784 Fax: (215) 244-9292 U.S. North Central Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. Northeast Phone: (978) 692-7660 Fax: (978) 692-8185 U.S. Northwest/Pacific West Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. South Central Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Southeast Phone: (770) 246-8283 Fax: (770) 246-0018 U.S. Southwest Phone: (949) 483-9119 Fax: (949) 483-9090 Europe Headquarters Conexant Systems France Les Taissounieres B1 1681 Route des Dolines BP 283 06905 Sophia Antipolis Cedex France Phone: (33 4) 93 00 33 35 Fax: (33 4) 93 00 33 03 Europe Central Phone: (49 89) 829 1320 Fax: (49 89) 834 2734 Europe Mediterranean Phone: (39 02) 9317 9911 Fax: (39 02) 9317 9913 Europe North Phone: (44 1344) 486 444 Fax: (44 1344) 486 555 Europe South Phone: (33 1) 41 44 36 50 Fax: (33 1) 41 44 36 90 Middle East Headquarters Conexant Systems Commercial (Israel) Ltd. P. O. Box 12660 Herzlia 46733, Israel Phone: (972 9) 952 4064 Fax: (972 9) 951 3924 Japan Headquarters Conexant Systems Japan Co., Ltd. Shimomoto Building 1-46-3 Hatsudai, Shibuya-ku, Tokyo 151-0061 Japan Phone: (81 3) 5371-1567 Fax: (81 3) 5371-1501 APAC Headquarters Conexant Systems Singapore, Pte. Ltd. 1 Kim Seng Promenade Great World City #09-01 East Tower Singapore 237994 Phone: (65) 737 7355 Fax: (65) 737 9077 Australia Phone: (61 2) 9869 4088 Fax: (61 2) 9869 4077 Taiwan Headquarters Conexant Systems, Taiwan Co., Ltd. Room 2808, 333 International Trade Building Keelung Road, Section 1 Taipei 110, Taiwan, ROC Phone: (886 2) 2720 0282 Fax: (886 2) 2757 6760 |
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